DIMMs Supported | Dell R610 guide

Dell™ PowerEdge™ R610 Technical Guidebook

Key features of the PowerEdge R610 memory system include:

•Registered (RDIMM) and Unbuffered (UDIMM) ECC DDR3 technology

•Each channel carries 64 data and eight ECC bits

•Support for up to 96GB of RDIMM memory (with twelve 8GB RDIMMs)

•Support for up to 24GB of UDIMM memory (with twelve 2GB UDIMMs)

•Support for 1066/1333MHz single- and dual-rank DIMMs

•Support for 1066MHz quad-rank DIMMs

•Single DIMM configuration only with DIMM in socket A1

•Support ODT (On Die Termination) Clock gating (CKE) to conserve power when DIMMs are not accessed

•DIMMs enter a low power self-refresh mode

•I2C access to SPD EEPROM for access to RDIMM thermal sensors

•Single Bit Error Correction

•SDDC (Single Device Data Correction – x4 or x8 devices)

•Support for Closed Loop

•Thermal Management on RDIMMs and UDIMMs

•Multi Bit Error Detection Support for Memory Optimized Mode

•Support for Advanced ECC mode Support for Memory Mirroring

B. DIMMs Supported

The DDR3 memory interface consists of three channels, with up to two RDIMMs or UDIMMs per chan- nel for single-/dual-rank and up to two RDIMMs per channel for quad rank. The interface uses 2GB, 4GB, or 8GB RDIMMs. 1GB or 2GB UDIMMs are also supported. The memory mode is dependent on how the memory is populated in the system:

Three channels per CPU populated identically.

In a dual-processor configuration, the memory configurations for each processor must be identical

•Typically, the system will be set to run in Memory Optimized (Independent Channel) mode in this configuration. This mode offers the most DIMM population flexibility and system memory capacity, but offers the least number of RAS (reliability, availability, service) features.

•Memory modules are installed in numeric order for the sockets beginning with A1 or B1

•All three channels must be populated identically.

•The first two channels per CPU populated identically with the third channel unused

•Typically, two channels operate in Advanced ECC (Lockstep) mode with each other by having the cache line split across both channels. This mode provides improved RAS features (SDDC support for x8-based memory).

•For Memory Mirroring, two channels operate as mirrors of each other — writes go to both channels and reads alternate between the two channels.

•For Memory Mirroring or Advanced ECC Mode, the three sockets furthest from the processor are unused and memory modules are installed beginning with socket A2 or B2 and proceeding in the following order: A2, A3, A5, and A6

•One channel per CPU populated

•This is a simple Memory Optimized mode. Mirroring is not supported.

The PowerEdge R610 memory interface supports memory demand and patrol scrubbing, single-bit correction and multi-bit error detection. Correction of a x4 or x8 device failure is also possible with SDDC in the Advanced ECC mode. Additionally, correction of a x4 device failure is possible in the Memory Optimized mode.

•If DIMMs of different speeds are mixed, all channels will operate at the fastest common frequency.

•RDIMMs and UDIMMs cannot be mixed.

•If memory mirroring is enabled, identical DIMMs must be installed in the same slots across both channels. The third channel of each processor is unavailable for memory mirroring.

•The first DIMM slot in each channel is color-coded with white ejection tabs for ease of installation.