Measurement Specialties PC-CARD-DAS16/12AO manual Triggering and transfer, Pacer clock

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PC-CARD-DAS16/12AO User's Guide

Functional Details

Triggering and transfer

Atrigger begins an acquisition/transfer cycle. There are three ways to trigger a PC-CARD-DAS16/12AO: programmable pacer, software, or external. The trigger source selection is programmable. The programmable pacer is the product of two 16-bit counters dividing a 10 MHz or 1 MHz pulse derived from a 10 MHz crystal oscillator which can be used to trigger any number of paced conversions. A single conversion can be triggered by software at any time. External trigger, pacer clock and interrupt signals may also be used to control conversions and synchronize to external events.

After a conversion is made, the sample is routed to a 4096-word (sample) FIFO buffer from which it may be retrieved one sample at a time or in blocks via REP-INSW transfers.

How do FIFO size and design affect throughput?

The 4096 12-bit sample FIFO buffer stores samples from the A/D converter as they are being converted. When a block of samples is ready and when the PC is ready, the FIFO is emptied into system memory. Most FIFO designs employ a half-full transfer initiation circuit. When the FIFO is half full, the transfer request is made. Samples continue to fill the second half of the FIFO while the CPU responds to the transfer request and transfers data to system memory.

A/D pacer clock

Many analog acquisitions can be handled by a simple on-board rate divider created by combining a crystal oscillator with a programmable counter. For those, the on-board 82C54 programmable rate generator (counter) supplies the pacing. Some applications require more flexible rate control.

The PC-CARD-DAS16/12AO analog conversions can be externally paced and thereby synchronized with events external to the PC. Conversions can be held off until some external event, such as a not-to-exceed condition is met. Conversions can be externally gated so that samples are taken only when an event of interest is occurring, such as a process going over normal limits.

Figure 9 shows a logic diagram of the A/D pacer clock and counters.

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Contents Page PC-CARD-DAS16/12AO Management committed to your satisfaction Trademark and Copyright Information Table of Contents PC-CARD-DAS16/12AO Users Guide What you will learn from this users guide Where to find more informationAbout this Users Guide Conventions in this users guideIntroducing the PC-CARD-DAS16/12AO Overview PC-CARD-DAS16/12AO featuresPC-CARD-DAS16/12AO block diagram ChapterSoftware features Hardware Installing the PC-CARD-DAS16/12AOWhat comes with your PC-CARD-DAS16/12AO shipment? Additional documentation Optional componentsInstalling the software Installing the PC-CARD-DAS16/12AO Unpacking the PC-CARD-DAS16/12AOIf your Pcmcia card is not detected Pin out I/O connector Connecting the board for I/O operationsConnectors, cables I/O connector Board connector, cables, and accessory equipmentCabling CPCC-50M-4 Field wiring and signal termination Calibrating the PC-CARD-DAS16/12AOProgramming and Developing Applications Programming languages Packaged applications programsRegister-level programming Functional Details Conversion speed and amplificationAnalog input ranges Triggering and transfer Pacer clockCounter/pacer logic diagram Absolute accuracy specifications SpecificationsAnalog input specifications Analog inputCrosstalk Channel to channel crosstalk specificationsNoise performance specifications Noise performanceDifferential linearity error ±0.5 LSB max Analog output sectionDigital input/output InterruptCounter Miscellaneous Power consumptionConnector and pin out EnvironmentalDifferential analog input mode pin out Single-ended analog input mode pin outDeclaration of Conformity USAMailinfo@mccdaq.com