Digital input/output
| Table 9. DIO specifications | |
|
|
|
Digital type |
| FPGA |
Number of I/O |
| 4 |
Configuration |
| One port, programmable |
|
| 4 input / 4 output |
Input low voltage |
| 0.8 V max |
Input high voltage |
| 2.0 V min |
Output low voltage (IOL = 4 mA) |
| 0.32 V max |
Output high voltage (IOH = |
| 3.86 V min |
Absolute maximum input voltage |
| |
| Input mode (high impedance) |
Interrupt
| Table 10. Interrupt specifications | |
|
|
|
Interrupts |
| Programmable: Levels 2 – 15 |
Interrupt enable |
| Programmable. Default = disabled. |
Interrupt sources |
| External (External Interrupt) |
|
| A/D |
|
| A/D |
|
| A/D |
|
| A/D Pacer |
Counter
Table 11. Counter specifications
Counter type | 82C54 |
|
Configuration | 3 down counters, 16 bits each | |
Counter 1 - User counter | Source: | Programmable external (Ctr 1 Clk) or 100kHz internal source |
| Gate: | Available at connector (Ctr 1 Gate), pulled to logic high via 10K |
| resistor. See Note 2. | |
| Output: | Available at connector (Ctr 1 Out) |
Counter 2 - ADC Pacer Lower Divider | Source: | Programmable, 1MHz or 10 MHz internal source |
| Gate: | Available at connector (A/D Pacer Gate), pulled to logic high |
| via 10K resistor. | |
| Output: | Chained to Counter 3 Clock |
Counter 3 - ADC Pacer Upper Divider | Source: | Counter 2 Output |
| Gate: | Internal |
| Output: | Programmable as ADC Pacer clock. Available at user connector |
| (ADC Pacer out) | |
Clock input frequency | 10 MHz max | |
High pulse width (clock input) | 30 ns min |
|
Low pulse width (clock input) | 50 ns min |
|
Gate width high | 50 ns min |
|
Gate width low | 50 ns min |
|
Input low voltage | 0.8 V max | |
Input high voltage | 2.0 V min |
|
Output low voltage | 0.4 V max | |
Output high voltage | 3.0 V min |
|
Crystal oscillator frequency | 10 MHz |
|
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