SOYO SY-7VCA2 user manual Chipset Features

BIOS Setup Utility SY-7VCA2

After you have completed the changes, press [Esc] and follow the

instructions on your screen to save your settings or exit without saving.

The following table describes each field in the Advanced Chipset Features

Menu and how to configure each parameter.

3-4.1 CHIPSET FEATURES SETUP

CHIPSET FEATURES

Bank 0/1, 2/3,

4/5 DRAM

Timing

Setting	Description	Note
SDRAM	This item allows you to select the	Default
8/10ns	value in this field, depending on
SDRAM	whether the board has paged
8ns	DRAMs or EDO (extended data
Normal	output) DRAMs.
Medium
Fast
Turbo

DRAM Clock

Host Clock	This item allows you to control the	Default
HCLK-33M
	DRAM speed.
HCLK+33M

SDRAM Cycle Length

2 When synchronous DRAM is Default

3installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer.

Bank
	4 Bank	Increase DRAM performance.	Default
Interleave	Disabled
	2 Bank
Memory Hole
	Disabled		Default
	Enabled	Some interface cards will map their
		ROM address to this area. If this
		occurs, select [Enabled] in this field.

P2C/C2P Concurrency

Disabled	This item allows you to
Enabled	enable/disable the PCI to CPU, CPU	Default
	to PCI concurrency

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