Socket Mobile IB810 user manual Advanced Bios Features, Virus Warning, CPU L1 and L2 Cache

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BIOS SETUP

Advanced BIOS Features

This section allows you to configure and improve your system and allows you to set up some system features according to your preference.

CMOS Setup Utility – Copyright © 1984-2001 Award Software

Advanced BIOS Features

 

 

 

 

 

 

Virus Warning

Disabled

ITEM HELP

 

 

CPU L1 and L2 Cache

Enabled

Menu Level

 

 

Quick Power On Self Test

Enabled

 

 

 

First Boot Device

Floppy

Allows you choose

 

 

Second Boot Device

HDD-0

the VIRUS warning

 

 

Third Boot Device

CDROM

feature for IDE Hard

 

 

Disk boot sector

 

 

Boot Other Device

Enabled

 

 

protection. If this

 

 

Swap Floppy Drive

Disabled

 

 

function is enabled

 

 

Boot Up Floppy Seek

Disabled

 

 

and someone

 

 

Boot Up Numlock Status

On

 

 

attempt to write

 

 

Gate A20 Option

Fast

 

 

data into this area,

 

 

Typematic Rate Setting

Disabled

BIOS will show a

 

 

Typematic Rate (chars/Sec)

6

warning message

 

 

Typematic Delay (Msec)

250

on screen and

 

 

alarm beep

 

 

Security Option

Setup

 

 

 

 

 

APIC Mode

Enabled

 

 

 

MPS Version Control for OS

1.4

 

 

 

OS Select For DRAM>64MB

Non-OS2

 

 

 

Report No FDD For WIN 95

No

 

 

 

Small Logo (EPA) Show

Enabled

 

 

 

 

 

 

 

 

 

 

 

 

Virus Warning

This item protects the boot sector and partition table of your hard disk against accidental modifications. If an attempt is made, the BIOS will halt the system and display a warning message. If this occurs, you can either allow the operation to continue or run an anti-virus program to locate and remove the problem.

CPU L1 and L2 Cache

Cache memory is additional memory that is much faster than conventional DRAM (system memory). CPUs from 486-type on up contain internal cache memory, and most, but not all, modern PCs have additional (external) cache memory. When the CPU requests data, the system transfers the requested data from the main DRAM into cache memory, for even faster access by the CPU. These items allow you to enable (speed up memory access) or disable the cache function. By default, these items are Enabled.

Quick Power On Self Test

When enabled, this field speeds up the Power On Self Test (POST) after the system is turned on. If it is set to Enabled, BIOS will skip some items.

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IB810 User’s Manual

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Contents USER’S Manual Version 1.0AAcknowledgments Table of Contents This page is intentionally left blank Introduction Product DescriptionChecklist Specifications BiosBoard Dimensions Installations Installing the CPU ATX Power Installation MicroPCI Daughter Card InstallationLock Installing the MemoryInstalling and Removing Memory Modules Top View of DDR SocketSetting the Jumpers Jumper Locations on IB810 Address Configuring the CPU FrequencyJP1 DiskOnChip Address Select RS-232 RS-422 RS-485 FunctionSW1 Lvds Resolution Select JP7 Clear Cmos ContentsJP8 Lvds Panel Power Select JP10, JP11, JP12, JP13, JP14 CRT VGA Signal SelectThis page was intentionally left blank Connectors on IB810 Connector Locations on IB810 Pin # Signal Name J1 System Function ConnectorSpeaker Pins 1 Power LED Pins 11Turbo LED Connector Pins 8 SMI/Hardware Switch Pins 6ATX Power on Switch Pins 7 Reset Switch Pins 9IDE1 Primary IDE Connector Signal Name Pin # J2 ATX 12V/+12V Power ConnectorIDE1, IDE2 Eide Connectors FAN2 System Fan Power Connector IDE2 Secondary IDE Connector Signal Name Pin #FAN1 CPU Fan Power Connector Signal Name Pin # FAN3 Auxiliary Fan Power ConnectorJ4 Floppy Drive Connector J5 Parallel Port Connector J7 Wake On LAN ConnectorJ8, J9 COM1, COM2 Serial Port J10 TV-Out ConnectorSignal Name Pin J11, J16 Lvds Connectors 2nd channel, 1st channel J15 Tmds Panel Connector on ID120 J12 External ATX Power ConnectorJ14 External Audio Connector J17 Panel Inverter Power ConnectorJ20 Smart Card Reader Interface J18, J19 USB ConnectorsPin Signal Name J21 IrDA Connector J22 External PS/2 Keyboard and Mouse ConnectorJ26 VGA CRT Connector J23 PS/2 Keyboard and Mouse ConnectorJ25, J27 Primary and Secondary RJ45 Connector Bios Setup Bios Introduction Bios SetupCmos Setup Utility Copyright 1984-2001 Award Software Standard Cmos Setup DateDrive a / Drive B TimeIDE Primary HDDs / IDE Secondary HDDs Video Halt OnVirus Warning Advanced Bios FeaturesQuick Power On Self Test CPU L1 and L2 CacheBoot Up Floppy Seek First/Second/Third Boot DeviceBoot Other Device Boot Up NumLock StatusMPS Version Control for OS Apic ModeSecurity Option OS Select for Dram 64MBAdvanced Chipset Features Video Bios Cacheable Dram Data Integrity ModeSystem Bios Cacheable Delayed TransactionAGP Aperture Size Delay Prior to ThermalICH2 ISA Enable IDE Primary/Secondary Master/Slave PIO Integrated PeripheralsOnChip Primary/Secondary PCI IDE IDE Primary/Secondary Master/Slave Udma IDE HDD Block ModePower On Function USB ControllerParallel Port Mode Uart Mode SelectUR2 Duplex Mode Pwron After PWR-FailAcpi Function Power Management SetupPower Supply Type Acpi Suspend TypePower Management Power On by Ring Suspend ModeHDD Power Down Resume by AlarmReload Global Timer Events Reset Configuration Data PNP/PCI ConfigurationsPNP OS Install Resources Controlled byPC Health Status Shutdown TemperatureTemperatures/Fan Speeds/Voltages Auto Detect PCI Clk Frequency/Voltage ControlCPU Clock Ratio Spread SpectrumSet Supervisor/User Password Load Fail-Safe DefaultsLoad Setup Defaults Save & Exit SetupDrivers Installation Intel Software Installation Utility Drivers Installation Drivers Installation Intel Ultra ATA Storage Driver Intel Ultra ATA Storage DriverDrivers Installation Drivers Installation Windows 98 Drivers Installation ATI M6 VGA Driver InstallationDrivers Installation Drivers Installation SigmaTel AC97 Audio Drivers Drivers Installation Drivers Installation PCI Ethernet Drivers Windows NT 4.0 Drivers Installation Drivers Installation Drivers Installation PCI Ethernet Drivers Windows 2000 Drivers Installation Drivers Installation Drivers Installation PCI Ethernet Drivers Address Device Description O Port Address Map Interrupt Request Lines IRQO Port Address Map Interrupt Request Lines IRQ Level Function