| | | | PCI32 Interface v3.0 |
| | | | |
| | | Table 1: Core Implementation (Continued) | |
| | | | |
| | | Supported Device | Power Supply |
| | | | |
| | | Spartan™-II XC2S30-PQ208-5C | 3.3V, 5.0V only |
| | | | |
| | | Spartan-II XC2S50-PQ208-5C | 3.3V, 5.0V only |
| | | | |
| | | Spartan-II XC2S100-PQ208-5C | 3.3V, 5.0V only |
| | | | |
| | | Spartan-II XC2S150-PQ208-5C | 3.3V, 5.0V only |
| | | | |
| | | Spartan-II XC2S200-PQ208-5C | 3.3V, 5.0V only |
| | | | |
| | | Spartan-IIE 2S50E-PQ208-6C | 3.3V only |
| | | | |
| | | Spartan-IIE XC2S100E-PQ208-6C | 3.3V only |
| | | | |
| | | Spartan-IIE XC2S150E-PQ208-6C | 3.3V only |
| | | | |
| | | Spartan-IIE XC2S200E-PQ208-6C | 3.3V only |
| | | | |
| | | Spartan-IIE XC2S300E-PQ208-6C | 3.3V only |
| | | | |
| | | Spartan-3 XC3S1000-FG456-4C/I (1) | 3.3V only |
| | | Spartan-3E XC3S1200E-FG400-4C/I | 3.3V only |
| | | | |
| | | Notes | |
1.Spartan-3 and Spartan-3E solution pending production speed files.
2.For additional Part/Package combinations, see the UCF Generator in the PCI Lounge.
3.XC2V1000 is supported over Military Temp. range
4.Spartan-3, Spartan-3E, and Virtex-4 devices do not contain TBUFs. The Xilinx tools automatically translate TBUFs to LUTs, and they are included in the worst case LUT count listed.
5.Virtex-II Pro, Virtex-4, Spartan-3, and Spartan-3E devices are supported over commercial and industrial temperature ranges.
6.As shipped, the core is verified for timing compliance with speedfile versions 1.56 and later. This applies to all production devices and most engineering samples. If you are using engineering samples that require the 1.54 speedfile, please contact Xilinx Customer Applications..
7.Requires 200 MHz reference clock.
Applications
•Embedded applications in networking, industrial, and telecommunication systems
•PCI add-in boards such as frame buffers, network adapters, and data acquisition boards
•Hot swap CompactPCI boards
•CardBus compliant
•Any applications that need a PCI interface
General Description
The Xilinx PCI interface is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are predefined. Critical paths are controlled by constraints and guide files to ensure predictable timing. This significantly reduces engineering time required to implement the PCI portion of your design. Resources can instead be focused on your unique user application logic in the FPGA and on the system-level design. As a result, Xilinx PCI prod- ucts minimize your product development time.
The core meets the setup, hold, and clock-to-timing requirements as defined in the PCI specification. The interface is verified through extensive simulation.
DS206 August 31, 2005 | www.xilinx.com | 3 |
Product Specification v3.0.151 | | |
