Xilinx PCI32 warranty Interface Configuration, Burst Transfer, Supported PCI Commands

PCI32 Interface v3.0

Target State Machine

This block controls the PCI interface target functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The target control logic uses one-hot encoding for maximum performance.

Table 2:	PCI Configuration Space Header
31		16 15				0
							00h
	Device ID			Vendor ID
							04h
		Status		Command
							08h
			Class Code		Rev ID
							0Ch
BIST			Header	Latency	Cache Line
			Type	Timer	Size
							10h
		Base Address Register 0 (BAR0)
							14h
		Base Address Register 1 (BAR1)
							18h
		Base Address Register 2 (BAR2)
							1Ch
		Base Address Register 3 (BAR3)
							20h
		Base Address Register 4 (BAR4)
							24h
		Base Address Register 5 (BAR5)
							28h
			Cardbus CIS Pointer
							2Ch
Subsystem ID				Subsystem Vendor ID
							30h
		Expansion ROM Base Address
							34h
			Reserved		CapPtr
							38h
			Reserved
							3Ch
Max Lat			Min Gnt	Int Pin	Int Line
							40h-FFh
			Reserved

Note: Shaded areas are not implemented and return zero.

Interface Configuration

The PCI Interface can be easily configured to fit unique system requirements using the Xilinx CORE Generator GUI or by changing the HDL configuration file. The following customization options, among many others, are supported by the interface and are described in the PCI User Guide.

•Device and vendor ID

•Base Address Registers (number, size, and type)

Burst Transfer

The PCI bus derives its performance from its ability to support burst transfers. The performance of any PCI application depends largely on the size of the burst transfer. Buffers to support PCI burst transfer can efficiently be implemented using on-chip RAM resources.

Supported PCI Commands

Table 3 illustrates the PCI bus commands supported by the PCI Interface.

6	www.xilinx.com	DS206 August 31, 2005
		Product Specification v3.0.151