BIOS Overview
PCI Interrupt Request Lines
PCI devices generate interrupt requests using up to eight PCI interrupt request lines. PCI interrupts can be shared; several devices can use the same interrupt. However, optimal system performance is reached when minimizing the sharing of interrupts.
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| Chipset |
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| PCI INT |
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| Internal | USB | USB | USB |
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| AGP | PCI1 | PCI2 | PCI3 | AC97 | controller | controller | controller | SMBus | ||
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| 1 | 2 | 3 |
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| PIRQA | INTA |
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| INTB |
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| PIRQB | INTB |
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| INTC |
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| PIRQC |
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| INTD |
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| PIRQD |
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| INTA |
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| PIRQE |
| INTD | INTC |
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| PIRQF |
| INTA | INTD |
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| PIRQG |
| INTB | INTA |
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| PIRQH |
| INTC | INTB |
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POST Tests
The POST is executed each time the system is powered on, or a reset is performed. The POST process verifies the basic functionality of the system components and initializes certain system parameters.
The POST starts by displaying a graphic screen of the
Devices, such as memory and newly installed hard disks, are configured automatically. The user is not requested to confirm the change. Newly removed hard disks are detected, and the user is prompted to confirm the new configuration by pressing F4.
NOTE The POST does not detect when a hard disk drive has been otherwise changed.
During the POST, the BIOS and other ROM data is copied into
The following table lists the POST checkpoint codes written at the start of each test:
Checkpoint | POST Routine Description | |
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D0 | NMI is Disabled. CPU ID saved. Init code Checksum verification starting. | |
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D1 | To do DMA init, Keyboard controller BAT test, start memory refresh and going to 4GB flat mode. | |
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D3 | To start Memory sizing. | |
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D4 | To comeback to real mode. Execute OEM patch. Set stack. | |
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D5 | E000 ROM enabled. Init code is copied to segment 0 and control to be transferred to segment 0. | |
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Evo D310 Micro Desktop 47