Motorola SC140 user manual Aa Bb Cc Dd

Page 13

Compiler Support on StarCore

The following instructions bring more than one byte at a time to the data register:

move.w (Rx), Dn move.f (Rx), Dn move.2w (Rx), Dh move.2f (Rx), Dh move.4w (Rx), Dk move.4f (Rx), Dk move.2l (Rx), Dh

Transfer one 16-bit word from memory (2 bytes) Transfer one 16-bit word from memory (2 bytes) Transfer two 16-bit words from memory (4 bytes) Transfer two 16-bit words from memory (4 bytes) Transfer four 16-bit words from memory (8 bytes) Transfer four 16-bit words from memory (8 bytes) Transfer two 32-bit words from memory (8 bytes)

where x spans from 0 to 15 and the data register notations are as follows:

•Dn represents D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, or D15.

•Dh represents D0:D1, D2:D3, D4:D5, D6:D7, D8:D9, D10:D11, D12:D13, or D14:D15.

•Dk represents D0:D1:D2:D3, D4:D5:D6:D7, D8:D9:D10:D11, or D12:D13:D14:D15.

Most processors require operands to be aligned in memory and multiple-operand load/stores to be aligned. For example, a double operand load requires an even address, and a quad operand load requires a double even address. These restrictions reduce the complexity of the address generation hardware, particularly for modulo addressing. For example, let us consider the move.4w (Rx), Dk instruction—more specifically, move.4w (R0),D0:D1:D2:D3 (four 16-bit words are moved from the memory address of R0 into the data registers D0, D1, D2, and D3, respectively). The data must align on an 8-byte boundary, so the address contained in R0 should be a multiple of eight. The examples in Figure 8 further illustrate this point.

.

 

 

 

 

 

 

 

 

 

Aligned

 

 

 

 

 

 

 

 

 

Not Aligned

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bringing one word from memory

 

 

 

 

 

 

 

 

 

 

move.w (r0),d0 where r0 = 0x0 or 0x2

 

move.w (r0),d0 where r0 = 0x1 or 0x3

 

P:0x00 AA BB CC DD

 

 

 

 

 

 

 

 

P:0x00

AA

 

 

BB

CC

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Aligned on a 2-byte boundary

 

 

 

 

 

Not Aligned on a 2-byte boundary

 

 

 

 

 

 

 

 

 

 

 

 

 

Correct Operation: brings either AABB

 

Erronenous Operation: brings wrong

(if R0 = 0x0) or CCDD (if R0=0x2)

 

 

 

 

data in d0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bringing two words from memory

 

 

 

 

 

 

 

 

 

 

move.2w (r0),d0:d1 where r0 = 0x0 or 0x4

 

move.2w (r0),d0:d1 where r0 = 0x1, 0x2 or 0x3

 

P:0x00

 

AA BB CC DD

 

 

 

EE

 

 

 

 

 

 

P:0x00

AA

 

BB

CC

DD EE

 

 

 

 

 

 

 

 

 

 

 

 

Aligned on a 4-byte boundary

 

 

 

 

 

Not Aligned on a 4-byte boundary

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Correct Operation: brings AABB CCDD

 

 

 

 

 

Erronenous Operation: brings wrong

(if R0 = 0x0)

 

 

 

 

 

 

 

 

data in d0:d1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 8.

 

Alignment Considerations

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Introduction to the SC140 Tools

 

 

 

 

 

13

Page 12 Page 14
Image 13
Page 12 Page 14
Contents Motorola Typical development process is represented in Figure Compiler Hands On File I/O ExerciseGood To Know Interpretation of 16-bit Integer and Fractional Data Values Integer and Fractional Arithmetic ExerciseInteger Arithmetic Compiler Support on StarCoreFractional Arithmetic Good To Know Local Optimization Local Versus Global Optimization ExerciseCompiler Support on StarCore StarCore C Compiler Global Optimization Local OptimizationMemory Alignment Exercise AA BB CC DD First Code Section Second Code Section Split Summation Exercise Code Generated Assembly Code = ∑ a i x n For 0 ≤ n L Multi-Sample ExerciseIntermediate Version Compromise Between Memory and Speed Further Speed Optimization Control Code The True Bit Exercise Save Ex7.c as Ex71.c Calling an Assembly Routine From C Exercise Current Following output should be displayed Challenge Introduction to the SC140 Tools Solutions to ExercisesAligned ExerciseExpected Motorola INC Intermediate version Compromise between Memory and Speed Compiler Support on StarCore Further Optimizing the Speed Compiler Support on StarCore Compiler Support on StarCore Motorola INC Zoffset equ Moffset equ Exercise Compiler Support on StarCore Compiler Support on StarCore AN2009/D
Top Page Image Contents