AMD K manual Preliminary Information

Page 12

Preliminary Information

AMD Athlon™ Processor Model 4 Revision Guide

23614K —October 2003

16INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain Linear Addresses

Products Affected. A4, A5, A6, A7, A9

Normal Specified Operation. After executing an INVLPG instruction the TLB should not contain any translations for any part of the page frame associated with the designated logical address.

Non-conformance.When the logical address designated by the INVLPG instruction is mapped by a 4- Mbyte page mapping and LA[21] is equal to one it is possible that the TLB will still retain translations after the instruction has finished executing.

Potential Effect on System. The residual data in the TLB can result in unexpected data access to stale or invalid pages of memory.

Suggested Workaround. When using the INVLPG instruction in association with a page that is mapped via a 4-Mbyte page translation, always clear bit 21.

Resolution Status. Fix planned for a future revision.

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Contents Revision Guide Advanced Micro Devices, Inc Revision History AMD Athlon Processor Model 4 Revision GuideAMD Athlon Processor Model Revision Guide Revision Guide PolicyProduct Errata Resolution Status. No fix planned Products Affected. A4, A5, A6, A7, A9Resistance Value of the ZN and ZP Pins Products Affected. A4, A5Potential Effect on System. The system hangs Instruction Execution Deadlock Products Affected. A4, A5, A6, A7Suggested Workaround. None Potential Effect on System. The system will hang Products Affected. A9 Preliminary Information Resolution Status. No fix planned Preliminary Information Preliminary Information Potential Effect on System. System failure Single Step Across I/O SMI Skips One Debug Trap Software Prefetches May Report a Page Fault Kernel WorkaroundPreliminary Information Revision Determination Technical and Documentation Support
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