Samsung S3F401F ARM7TDMI-S FLASH-ROM Core, Interrupt Sram, Controller TAP Controller PLL, UART0/1

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EVALUATION BOARD MANUAL	S3F401F_BD_UM_REV1.00

Crystal or Ceramic Oscillator

	AHB
ARM7TDMI-S	FLASH-ROM
CORE	256KB
INTERRUPT	SRAM
INTERRUPT	20KB
CONTROLLER
	TAP CONTROLLER
PLL	For JTAG
PLL
	BRIDGE

CLOCK

MONITOR

I/O

CONTROLLER

BT & WDT

12-BIT ADC


	IMC0/1				ENC0/1

SSP0/1

TIMER 0/1/2/3/4/5

APB

UART0/1

Figure 1. S3F401F Block Diagram

2

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Contents Evaluation Board Manual S3F401F Table of Contents Evaluation Board Manual ARM7TDMI-S FLASH-ROM Core Interrupt SramController TAP Controller PLL Clock Monitor Controller BT & WDT BIT ADCFeatures SW6Uart LEDBoard Components Configuration Power Block Detailed Block ConfigurationsCN1 VIN CN2 GND Normal Mode Setting Block J9 & J10 & J11 Jumper Setting MD20Spgm Uart Block TXD0RXD0 TXD1Evaluation Board Manual SSP Block SW7 on SW8 onEvaluation Board Manual 5 7-SEGMENT Block IMC Block ⑥ 2 ADC BlockBlock Symbols Description Function BlocksDescription Default Setting Jumper Connection JP#AIN0~AIN14 SW3INPUTJumper Connection MOTOR1MOTOR2 GND VCCSwitches SW# S3F401F-EVB REV 1.0 Board Schematics SCH-01 SCH-02 SCH-03 SCH-04 SCH-05 SCH-06 SCH-07 SCH-08 SCH-09 SCH-10 SCH-11