2.2.1Block Diagram (Segment Driver)
CS R/W | D/I | E DB0 to DB7 |
RST VDD VSS VLC |
|
|
|
|
|
|
|
|
| 8 | Segment Driver |
|
|
|
|
|
|
|
| Interface Control |
|
|
|
|
| Input and Output Buffer |
| ||
|
| Busy Flag |
|
|
|
|
|
|
|
|
|
|
| 8 |
| 8 |
|
|
|
|
|
| Output |
| Input | Instruction Register |
|
|
|
|
| Register |
| Register |
|
|
|
|
| 6 |
|
|
| 9 |
|
|
|
|
|
|
|
| |
| Display ON/OFF | Display Start Line |
| 8 | X, | |||
|
| Register |
|
| Counter | |||
|
|
|
|
|
| |||
|
|
| 6 |
|
| 8 |
| 9 |
|
|
|
|
|
|
|
| |
|
|
|
|
| Display Data RAM | |||
|
| Counter |
| 6 |
| 4096 bit |
| |
|
|
|
|
|
|
| 64 |
|
|
|
|
|
|
|
| Display Data Latch | |
|
|
|
|
|
|
| 64 |
|
|
|
|
|
| 4 |
| LC Driver |
|
|
|
|
|
|
|
|
| |
1 | 2 | FRM | CL | Va | M | Y2 |
| Y64 |
|
|
|
| Vc | Y1 |
| ||
|
|
|
| Vd |
|
|
|
|
|
|
|
| Vf |
|
|
|
|
Figure 3 Segment Driver
- 8 -