Sony S530D manual Communications from IC202 to Other ICs, Communications from Another IC to IC202

Address Lines

Direct Addressing

The parallel bus in this unit contains multiple address lines to designate the destination of the data within the IC that is chip selected. These ad- dress lines are labeled A0-21 from master IC202. Address lines are shared by some destination ICs and none use all 22 address lines.

Column and Row Addressing

IC401 and IC303 control three memory ICs. A memory IC has more data locations than can be accessed by one set of address lines directly. CAS and RAS lines are used to expand that number. Memory locations can be addressed like cells in a multiplication table. For example, when CAS is active, the address lines identify a column of memory locations. Then when RAS is active, the address lines now pin point the memory cell by identifying the row it is in.

Data and Clock Lines

Serial data communications involve the fewest number of connections between ICs. When speed is important, the parallel data structure is used. Instead of having a single data line between the communicating ICs, there are 8 or 16 lines that carry data. As in the serial bus structure, on a separate line the parallel bus uses a bit clock signal. When a single bit clock pulse occurs, the entire group of 8 or 16 bits of data is transferred at once. Therefore, the data transfer rate of the parallel bus system is much faster than the serial bus.

Interrupt Lines

Interrupt signals are used when the destination IC has carried out the instruction given to it and wants to reply with resultant data (such as task completed or information such as AC-3 detected). A destination IC can not generate a clock or chip select lines to send data to the master IC202. The destination IC must send an interrupt signal to the master IC202 requesting attention. When the master IC202 is ready, it will send chip select and clock signals, allowing the destination IC to send data.

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Read / Write Lines

Bi-directional communications on the parallel bus may use a single write enable (WE) / read enable (RE) line from the master IC202. During the chip select interval, this line determines the direction of the data to or from the master IC202. A high is one data direction while a low is the other. In some systems, two individual read and write lines are used.

When there are no interrupt, WE or RE lines, communications are pre- established to share the time to read and write during the chip select interval.

Communications from IC202 to Other ICs

IC202 can only send data to another IC after it chip selects the IC and supplies internal address and bit clock to carry the data. Consequently, a list of communications from IC202 would consist of the following:

·Chip Select (usually active low)

·Write control line (usually active low)

·Address data (Identifies the registers/memory location in the destina- tion IC to put the data)

·Bit clock

·Data

Communications from Another IC to IC202

If another IC has finished a task and wants to reply with sensor informa- tion, it must request the service (signals) above to return data. Once the destination IC sends an interrupt pulse, IC202 will reply with all the sig- nals listed above so the other IC can send data to IC202.

The Read control line (from IC202) is active instead of the write line in the date reply to IC202. All or some of the address locations are checked by IC202. The number is dependent upon the firmware built into Syscon IC202. For example, IC202 may request the Servo IC701 perform a sled movement to home task. Later IC202 receives an interrupt from IC701. Instead of checking all of IC701’s address locations, it will just access the one that contains the sled at home data.