Toshiba SD-R6112 specifications 18/28, Shows the Host Interface DMA multi word Timings

6.2.3.Timing of Host Interface (DMA Multi)

Figure 14 shows the Host Interface DMA multi word Timings

t0

DMARQ

		tL
DMACK-*1		tK
tI	tD
		tJ
DIOR-/DIOW-*1
Read	tE	tZ
DD0-15
		tF
Write
DD0-15
	tG	tH

*1: In all timing diagrams, the low line indicator negated, and the upper line indicators asserted.

	Multi word DMA	Min time (ns)	Max time (ns)
	timing parameters min(ns) max(ns)
t0	Cycle time	120
tC	DMACK to DMREQ delay		---
tD	DIOR-/DIOW-16-bit	70
tE	DIOR- data access		---
tF	DIOR- data hold	5
tZ	DMACK- to tristate		25
tG	DIOR/DIOW- data setup	20
tH	DIOW- data hold	10
tI	DMACK to DIOR-/DIOW- setup	0
tJ	DIOR-/DIOW- to DMACK hold	5
tKr	DIOR- negated pulse width	25
tKw	DIOW- negated pulse width	25
tLr	DIOR- to DMREQ delay		35
tLw	DIOR- to DMREQ delay		35

Figure 14 Host Interface Timing (Multi Word DMA Mode 2)

18/28 SD-R6112 Rev.1.0