Sanyo EP93F manual LC72723/M, LC72720Y/YV

❋ :CCB is SANYO's original bus format. All bus addresses are managed by SANYO for this format.

RDS Demodulator ICs

LC72723/M

Overview

The LC72723 and LC72723M are Radio Data System (RDS) demodulation and signal-processing ICs.

These ICs integrate a bandpass filter, the demodulation circuit, and data buffer RAM on the same chip and allow the RDS data to be read out in slave mode operation with an externally provided clock input signal.

(Master mode operation, in which the data is output in synchronization with the internal RDS clock output, is also supported.)

Functions

■Bandpass filter: switched capacitor filter (SCF)

■RDS demodulation: 57 kHz carrier regeneration, clock regeneration, biphase and differential decoding

■Buffer RAM: 128 bits (about 100 ms)

■Data I/O: Data readout in either master or slave mode

■RDS ID detection: Supports ID reset

■Standby mode: The crystal oscillator is stopped

■Fully adjustment free

■Packages:(LC72723) : DIP16(300mil)

(LC72723M) : MFP16(225mil)

Block Diagram

+5V	VREF	FLOUT	CIN	+5V
Vdda				Vddd
				CLOCK

Single-Chip RDSDS SignalSignal--ProcessingProcessingSystemSystem ICIC

LC72720Y/YV

Overview

The LC72720Y and LC72720YV are single-chip system ICs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RDBS (Radio Broadcast Data System) standard. These ICs include band-pass filter, demodulator, synchronization, and error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision error correction technique.

Functions

■Band-pass filter: Switched capacitor filter (SCF)

■Demodulatior: RDS data clock regeneration and demodulated data reliability information

■Synchronization: Block synchronization detection (with variable backward and forward protection conditions)

■Error correction: Soft-decision/hard-decision error correction

■Buffer RAM: Adequate for 24 blocks of data (about 500 ms) and flag memory

■Data I/O: CCB interface (power on reset)

Features

■Error correction capability improved by soft-decision error correction

■The load on the control microprocessor can be reduced by storing decoded data in the on-chip data buffer RAM

■Two synchronization detection circuits provide continuous and stable detection of the synchronization timing

■Data can be read out starting with the backward-protection block data after a synchronization reset

■Fully adjustment free

■Low voltage (supply voltage: 3.0 V min) type

■Operating power-supply voltage: 3.0 to 3.6 V

■Operating temperature: -40 to +85°C

■Packages: (LC72720Y) : DIP24S(300mil)

(LC72720YV) : SSOP30(275mil)

Block Diagram

			+	PLL	RECOVERY
	REFERENCE		-	(57kHz)
					(1187.5Hz)
	VOLTAGE
Vssa						Vssd
			VREF
		57kHz
MPXIN	ANTIALIASING	BPF	SMOOTHING		DATA	RDDA
		(SCF)
	FILTER		FILTER		DECODER
						RDCL
					RAM	MODE
					(128 bit)
			CLK(4.332MHz)			RST
						RDS-ID/
TEST	TEST				RDS-ID
						READY
				OSC	DETECT
			XIN	XOUT

+3.3 V		VREF	FLOUT	CIN
Vdda				+			CLOCK
					PLL
	REFERENCE			-	(57kHz)	RECOVERY
						(1187.5Hz)
Vssa	VOLTAGE
			VREF
		57kHz
MPXIN	ANTIALIASING	BPF	SMOOTHING				DATA
		(SCF)
	FILTER		FILTER			DECODER
DO			RAM	ERROR CORRECTION
CL	CCB					SYNC/EC CONTROLLER
		(24 BLOCK DATA)		(SOFT DECISION)
DI
CE
T1		MEMORY CONTROL		CLK(4.332MHz)
	TEST					SYNC		SYNC
T2
						DETECT-1		DETECT-2
T3 to T7				OSC/DIVIDER
				XIN	XOUT

+3.3 V

Vddd

Vssd

RDS-ID

SYNC SYR

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