Panasonic PT-50LC13 service manual SD/PC Card Signal Process Block Diagram, IC9008, IC9002, Q9001

SD/PC CARD SIGNAL PROCESS BLOCK DIAGRAM
MAIN C.B.A.																											CARD Y/PB/PR SIGNAL
								IC9004 (SD/PC CARD SIGNAL PROCESS)																			L9012	P9002
																										+3.3V		VCC(+3.3V)
											160-162,165			SD DATA(0-3)														SD DATA(0-3)
																													SD CARD
																												SD CLOCK
											SD CLOCK 169
																											SD WRITE PROTECT(L)
				CARD Y/PB/PR DATA (8BIT) : 480i
								106-110,																				SD CARD DETECT(L)
		CARD Y/PB/PR DATA																			IC9207 (TRANSCEIVER)
	TO VIDEO I							113-115
		(0-7)									SD/PC CARD
	SIGNAL PATH	CARD V-SYNC							CARD V-SYNC												2				18
	BLOCK DIAGRAM							118			SIGNAL PROCESS
																					3				17
		CARD H-SYNC						119	CARD H-SYNC																			P9201
																					4				16
											122-128,131-137,			PC DATA(0-15)							5				15			PC DATA(0-15)
											140,141										6				14			PC ADDRESS(0-9)
																					7				13
																					8				12		PC CARD DETECT1(L)
																					9				11		PC CARD DETECT2(L)
																					1	DIRECTION						CHIP ENABLE2
																					19	ENABLE		VCC 20				CHIP ENABLE1
																												OUTPUT ENABLE	PC CARD
						IC9008																						I/O READ CONTROL
										1,18,27,51,59,68,75,92,																		WRITE ENABLE
							+3.5V			99,104,111,130,148,157,																		I/O WRITE CONTROL
					+6.5V	3		2	VCC	159,164,183,193,201											IC9208 (TRANSCEIVER)							VS1
							REG.
																												VS2
																					2				18			REG
																					3				17			RESET(L)
																					4				16
																					5				15
																					6				14
																					7				13
																					8				12				+5V(PC CARD DETECTED)/0V(NO PC CARD)
																					9				11
						IC9002															1	DIRECTION
							+2.8V			9,35,44,83,121,139,172											19	ENABLE
					+3.3V	2		3	VCC															VCC 20
							REG.
							4
											PC ADDRESS 0 154														+3.3V
																					IC9209 (BUFFER)
											PC ADDRESS 1 155
							Q9001
														IC9205 (D-FLIP/FLOP)							2				18
																					3				17
														3	F/F		2				4				16
														4	F/F		5				5				15
														7	F/F		6				6				14
														8	F/F		9				7				13
														13	F/F		12				8				12
														14		F/F	15				9				11
IC9001 (128M SDRAM)														17		F/F	16				19	ENABLE		VCC
														18		F/F	19							20
																	11
				SDRAM DATA (0-15)									+3.3V	20	VCC
	128M SDRAM							77-82,85-90,													IC9211 (BUFFER)
																								20
						TP9001		93-96
																								VCC
		94.5MHz	38					102	94.5MHz												2				18
														IC9201 (D-FLIP/FLOP)
	1,3,9,14,27,43,49																				3				17
																					4				16
		VCC		+3.3V									+3.3V	16	VCC						5				15
																					6				14
																					7				13
														11	F/F		10				8				12
														13	F/F		12				9				11
														14		F/F	15				19	ENABLE
											CARD RESET(L) 24			1					IC9206 (OR GATE)
											LCS1(L) 174			9					1
																			3
																			2				IC9204 (+5V REG.)		TP9202
																			4
																			6
													+3.3V	IC9202 (D-FLIP/FLOP)					5			+6.5V	1	+5V REG.	3
																			10
														1					8
																			9					2
														2
															F/F		5		VCC 14	+3.3V
														3								TP9201		PC CARD ON(H)
														4
														10
											HCS3(L) 153			11	F/F		9
														12
											HRD 150			13		VCC
																14
														IC9203 (2 TO 4LINE DECODER)			+3.3V				IC9212 (BUFFER)
																16
			IC9003 (INVERTER)											1		VCC	4				1
															2 TO 4LINE						2			4
											IO/MEM 158			2
															DECODER
														3			5
														13	2 TO 4LINE		11
TO VIDEO I														14
															DECODER						IC9210 (BUFFER)
	27MHz CLOCK		12	13				116	27MHz CLOCK		HWR 149			15			12							20
SIGNAL PATH
BLOCK DIAGRAM	X9001																							VCC
																					2				18
			1		11		10	117	27MHz CLOCK
																					3				17
	27MHz
											HCS1(L) 152										4				16
	OSC																			DATA(8-15)	5				15
			2		9		8	105	27MHz CLOCK
														IC9007 (FLASH MEMORY)							6				14
																					7				13
			3	4	5		6	49	27MHz CLOCK												8				12
												DATA(0-15)	DATA(0-7)			PROGRAM FOR					9				11
											178-182,185-191,				FLASH
											194-197				MEMORY	CARD PROCESSOR (IC9004)		VCC 37	+3.3V		19	ENABLE
														12	RESET(L)
		+3.3V	14	VCC
											LCS2(L) 175							CARD RESET(L) <FROM IC6003(43)>							CARD SERIAL DATA 0
											CARD SERIAL DATA 1 142														CARD SERIAL DATA 1	TO/FROM
											CARD SERIAL CLOCK 143														CARD SERIAL CLOCK	SYSTEM CONTROL
											CARD CS(L) 166														CARD CS(L)	BLOCK DIAGRAM
											CARD READY(L) 167														CARD READY(L)

SD/PC CARD SIGNAL PROCESS BLOCK DIAGRAM

PT-50LC13