Icom IC-V8000 service manual PLL Circuits, Power Supply Circuits

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT (MAIN AND LOGIC UNITS)

A PLL circuit provides stable oscillation of the transmit fre- quency and receive 1st LO frequency. The PLL output com- pares the phase of the divided VCO frequency to the refer- ence frequency. The PLL output frequency is controlled by the divided ratio (N-data) of a programmable divider.

An oscillated signal from the TX and RX-VCO circuits pass- es through the LO and buffer amplifiers (Q9, Q12) is applied to the PLL IC (IC1, pin 6) and is prescaled in the PLL IC based on the divided ratio (N-data). The reference signal is generated at the reference oscillator (X1) and is also applied to the PLL IC. The PLL IC detects the out-of-step phase using the reference frequency and outputs it from pin 15. The output signal is passed through the loop filter(Q2) and is then applied to the TX and RX-VCO circuits as lock volt- age.

The lock voltage is also used for the receiver tunable band- pass filters to match the filter’s center frequency to the desired receive frequency. The lock voltage is passed through the loop filter (Q2), and then applied to the DC amplifier (Q10). The amplified signal is applied to the CPU (LOGIC unit; IC7, pin 98) via the “LVIN” signal. The signal is analyzed at the CPU, and then applied to bandpass filters (D9–D11, D13) as “T1”, “T2”, “T3” signals via the D/A con- verter.

4-3-2 VCO CIRCUIT (MAIN UNIT)

The VCO circuit contains a separate TX-VCO (Q6, D2, D4) and RX-VCO (Q7, D5). The oscillated signal is amplified at the LO (Q9) and buffer (Q11) amplifiers, and is then Tx/Rx switching circuit (D6, D7). Then Tx and Rx signals are applied to the pre-driver (Q17) and 1st mixer circuit (Q19) respectively.

A portion of the signal from LO amplifier (Q9) is amplified at the buffer amplifier (Q12) and is then fed back to the PLL IC (IC1, pin 6) as the comparison signal.

4-4	POWER SUPPLY CIRCUITS
VOLTAGE LINE
LINE		DESCRIPTION
HV		The voltage from the power supply.
		The same voltage as HV line which is controlled
		by the HVSW circuit (Q28, Q30, Q31). When the
		[POWER] switch is pushed, the CPU outputs the
SWHV		“PWRON” control signal via the expander IC
		(IC2). The signal is applied to the HVSW circuit
		to turn the circuit ON.
		The output voltage is applied to the drive ampli-
		fier (Q18), +8V regulator circuit (IC7), etc.
		Common 5 V for the CPU converted from the HV
		line by the C5V regulator circuit (IC8). The circuit
		outputs the voltage regardless of the power
C5V		ON/OFF condition.
		The output voltage is applied to the EEPROM
		(LOGIC UNIT; IC5), CPU (LOGIC UNIT; IC7),
		etc.
		Common 8 V converted from the 13.8 V line by
+8V		the +8V regulator circuit (IC7).
		The output voltage is applied to the LO (Q9) and
		buffer (Q11) amplifiers, etc.
+5V		Common 5 V converted from the +8 V line by the
		+5V regulator circuit (Q21, Q22).
		Transmit 8 V controlled by the T8V regulator cir-
T8		cuit (Q14, Q15) using the “TXC” signal from the
		I/O expander IC (IC2).
		Receive 5 V controlled by the R5V regulator cir-
		cuit (Q25) using “RXC” signal from the I/O
R5V		expander IC (IC2).
		The output voltage is applied to the FM IC IC
		(IC4), IF (Q16) and RF (Q27) amplifiers, etc.

• PLL CIRCUIT

		TX VCO		to transmitter circuit
			Q11
		Q6,		D6
			Buff.
		D2,		to 1st mixer circuit (Q19)
		D4	Q9
		RX VCO	LO	D7
			Q12
		Q7,		TX/RX
Loop			Buff.	switch
	Q2	D5
filter			IC1 (PLL IC)

9	Phase	Programable		Prescaler	6
	detector	divider
	Reference				2	PLLCK
X1			Shift register		3
						PLLDATA
25.25 MHz	divider				4	PLLSTB
1
				25.25 MHz 2nd LO signal
				to the 2nd IF IC (IC4, pin 2)

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