Intel LXD386 manual

Page 20

20

31

31

31

Figure

5.0

LXD386—

CON1A

CON1B

CON1C

32

a32

LOOP1/D1

32

b32

32

c32

LOOP0/D0

a31

LOOP3/D3

b31

c31

LOOP2/D2

30

a30

DLOOP1/D5

30

b30

30

c30

DLOOP0/D4

9.EvaluationBoardSchematic—Data/Control

EvaluationBoardforQuadT1/E1Applications

a29

DLOOP3/D7

b29

c29

DLOOP2/D6

A4

0VCC

1VCC

2VCC

3VCC

VCCIO DIGVCC ANAVCC

EvaluationBoardSchematics

29

29

29

a28

A1

b28

c28

A0

28

28

28

a27

A3

b27

c27

A2

27

27

CS

27

a26

b26

c26

A4

26

26

26

a25

b25

c25

25

25

25

a24

b24

c24

R1

24

24

24

a23

b23

c23

23

23

23

4.7K

a22

b22

c22

22

22

22

a21

b21

c21

VCC

21

21

21

a20

b20

c20

20

20

20

a19

b19

c19

19

19

19

R/W/RD

a18

b18

c18

18

18

18

a17

b17

c17

R2

17

17

TRST

17

a16

b16

c16

16

16

16

a15

b15

TMS

c15

10K

VCC

15

15

15

a14

b14

TCK

c14

14

14

14

MODE

a13

b13

TDO

c13

13

VCC

13

13

a12

b12

TDI

c12

VCC

12

a11

12

b11

INT

12

c11

JP1

11

11

11

a10

b10

c10

R3

10

10

10

a9

b9

c9

9

9

9

10K

a8

b8

c8

C1

.1uF

8

8

8

a7

b7

c7

7

7

7

a6

b6

c6

6

6

6

a5

b5

c5

C2

.1uF

5

5

5

a4

b4

c4

4

ALE/SCLK/AS

4

4

CLKE

a3

b3

c3

3

3

3

a2

MOT/INTL

b2

c2

ACK/RDY/SDO

C3

.1uF

2

2

2

a1

MUX

b1

c1

DS/WR/SDI

1

1

1

96 Pin DIN Connector Male

96 Pin DIN Connector Male

96 Pin DIN Connector Male

C4

.1uF

C5

.1uF

C6

.1uF

VCC

R4

U1A

8 9 68 67 4 6 75

10K

MCLK

78

MCLK

79

25

MODE

MODE

LOS0

LOS0

84

18

MUX

CLKE

CLKE

LOS1

LOS1

MUX

99

58

MUX

LOS2

LOS2

MOT/INTL

1

51

MOT/INTL

MOT/INTL

LOS3

LOS3

A0

85

A0

A1

86

A1

A2

87

A2

A3

88

A3

A4

89

R/W/RD

R/W/RD

2

R/W/RD

CS

98

CS

CS

OE

83

OE

OE

ALE/SCLK/AS

82

ALE/SCLK/AS

ALE/SCLK/AS

JTAG PORT

DS/WR/SDI

3

DS/WR/SDI

DS/WR/SDI

INT

80

INT

ACK/RDY/SDO

81

ACK/RDY/SDO

JP2

90

72

TRST

LOOP0/D0

LOOP0/D0

TRST

1

2

91

71

TMS

LOOP1/D1

LOOP1/D1

TMS

3

4

R5

R6

R7

R8

R9

R10

92

69

TCK

LOOP2/D2

LOOP2/D2

TCK

5

6

93

73

TDO

100K

100K

100K

100K

100K

100K

LOOP3/D3

LOOP3/D3

TDO

7

8

94

70

DLOOP0/D4

LOOP4/D4

TDI

TDI

95

HEADER 4X2

DLOOP1/D5

LOOP5/D5

GNDIO DIGGND ANAGND

96

0GND

1GND

2GND

3GND

77

AT1

DLOOP2/D6

LOOP6/D6

AT1

97

76

AT2

DLOOP3/D7

LOOP7/D7

AT2

Developer

LXT386

10 11 66 65 5 7 74

R11

R12

100K

100K

LEVEL ONE COMMUNICATIONS

Title

FIREBIRD - LXD386

DEMO BOARD

Size

Document Number

Rev

B

DATA/CONTROL

A4

Manual

Date:

Wednesday, September 15, 1999

Sheet

1

of

6

Image 20

Contents LXD386 Evaluation Board for Quad T1/E1 Applications Developer ManualPage Contents Figures TablesFeatures General DescriptionLXD386 Evaluation Board for Quad T1/E1 Applications Overview LXD386 Packing ListEquipment Requirements Control ModesFactory Settings Hardware Mode Set-Up and Operation Power ConnectionsHardware Mode Selection Loopback Mode SelectionOutput Enable Selection Code SelectionMonitoring Address Selection Jitter Attenuator SelectionMaster Clock Setup Line Buildout SelectionJtag Boundary Scan Port Framer/ASIC ConnectionBoard Protection LED IndicatorsLine Interface Software Mode Set-Up and Operation I8051 Microcontroller BoardEvaluation Board Set-up Test Equipment ConnectionsSoftware Installation and Start-Up Evaluation Board SoftwareHardware Set-up Screen Quitting the ProgramConfiguration Screen Communications Modes Apply to all Channels Setting Registers Registers ScreenRegisters Screen LXD386 Interface Unit Evaluation Board Applications Firebird LXD386 For