Digital Signal Processor (HG51A115A01FD)
Upon receipt of note numbers and their velocities, the DSP reads sound and velocity data from the sound source ROM in accordance with the selected tone; the DSP can read rhythm data simultaneously when a rythm pattern is selected. Then it provides
The following table shows the pin functions of the DSP.
Pin No. | Terminal | In/Out | Function | |
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1 ~ 8 | CD0 ~ CD7 | In/Out | Data bus | |
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9, 10 |
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| Not used. | |
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11 | GND7 | In | Ground (0V) source | |
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12 | CK16 | Out | 16.384MHz clock output | |
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13 | VCC6 | In | +5V source | |
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14 | CK0 | In | Clock input. Connected to terminal CK16. | |
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15 | TCKB |
| Not used. | |
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16 | VCC1 | In | +5V source | |
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17 | GND1 | In | Ground (0V) source | |
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18, 19 | XT0, XT1 | In/Out | 16.384MHz clock input/output. Connected to a crystal oscillator. | |
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20 | SGL | In | System control terminal. Single chip system: Open | |
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21 | CCSB | In | Chip select signal input | |
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22 ~ 25 | CA0 ~ CA3 | In | Addess bus | |
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26 | CE0 | In | Not used. Connected to ground. | |
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27 | CWRB | In | Write enable signal | |
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28 | CRDB | In | Read enable signal | |
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29 ~ 32 |
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| Not used. | |
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33 | RESB | In | Reset signal input | |
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34 | TESB | In | Not used. Connected to +5V. | |
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35 ~ 39 |
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| Not used. | |
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40 ~ 49 | RD0 ~ RD15 | In | Data bus for the sound source ROM | |
52 ~ 57 | ||||
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58 | RA23 | Out | Not used. | |
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59 | RA22 | Out | Chip select signal for the sound source ROM | |
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60, 61 | RA20, RA21 | Out | Not used. | |
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62 ~ 73 | RA0 ~ RA19 | Out | Data bus for the sound source ROM | |
75 ~ 82 | ||||
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74 | GND5 | In | Ground (0V) source | |
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83 | WOK2 | Out | Word clock output. Not used. | |
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84 | VCC3 | In | +5V source | |
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85 | GND3 | In | Ground (0V) source | |
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86 | WOK1 | Out | Word clock for the DAC | |
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87 | SOLM | Out | Serial data output. Not used. | |
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88 | SOLP | Out | Serial data output for the DAC | |
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89 | BOK | Out | Bit clock output for the DAC | |
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90 ~ 92 |
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| Not used. | |
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— 8 —