What SPI clocking modes does the MAX3420E support?

By setting a control bit (FDUPSPI, full-duplex SPI), the MOSI and MISO data appear on separate pins, providing a 4-wire interface. Finally, an INT (interrupt out) pin can be connected to a processor's interrupt system.

3.What SPI clocking modes does the MAX3420E support?

The SPI mode is usually expressed in the form (x,y) where one variable is the clock polarity, CPOL, and the other is the clock phase, CPHA. The MAX3420E operates in modes (0,0) or (1,1) without requiring a mode bit. The only difference between these modes is the inactive SCLK level: low for (0,0), high for (1,1). There are two basic requirements for running the MAX3420E SPI interface:

■MOSI data supplied to the MAX3420E must be valid before the first positive SCLK edge.

■SPI input data is sampled on the positive edge of the clock, and output data changes on the negative edge of SCLK.

Be careful with these modes—some microprocessor data sheets do not adhere to the (0,0) and (1,1) convention. It is best to verify the above two points when setting a clock mode. Also see the MAX3420E data sheet and MAX3420E Programming Guide for SPI example waveforms.

4.My CPU uses a 2.5V supply, but the MAX3420E uses a 3.3V VCC supply. Do I need

external level translators?

No. The MAX3420E contains internal level shifters. A VL pin powers the internal logic and serves

as the logic reference voltage for the SPI and IO pin signals. For a 2.5V interface, connect your 2.5V supply to the VL pin. The VL pin can actually operate with a range of voltages from 1.7V to 3.6V. If the controller uses 3.3V, tie VL to VCC.

5.What is the purpose of the MAX3420E INT pin?

The INT pin goes active whenever the MAX3420E requires service. During USB peripheral operation, this includes the arrival of SETUP, IN or OUT packets, plus bus events like bus reset, suspend, and resume. Using this pin in a system reduces the SPI traffic since the interrupt request bits do not need to be polled over the SPI interface.

6.Does the MAX3420E support active-low wired-OR interrupts? How about edge active interrupts?

The MAX3420E supports both interrupt types, using a control bit called INTLEVEL. Setting INTLEVEL=1 makes the INT output pin open-drain, active-low for wired-OR applications. This mode requires an external pullup resistor to VL. Setting INTLEVEL=0 (the default value) makes

the INT pin edge-active with a push-pull output driver. In edge mode, a second bit called POSINT sets the edge polarity to positive or negative.

7.How fast can I run the MAX3420E SPI interface (SCLK max frequency)?

With VL of 2.5V or greater, the SCLK signal can be as high as 26MHz. For lower VL values, the data sheet shows how much to derate the SCLK maximum frequency.

8.Is there a low limit to the MAX3420E SCLK frequency?

No. This clock can be held high or low indefinitely. Also, the MAX3420E ignores SCLK transitions while SS# is high.

9.I have an 8-pin microprocessor, and it takes 5 of its' IO pins to connect to the MAX3420E. How do I do IO?

The MAX3420E has four general-purpose outputs (GPOUT3-0) and four general-purpose input pins (GPIN3-0) that are set and read using the IOPINS register, R20. This replaces the microcontroller pins used to implement the SPI interface, and provides additional ones.

10.Do I need to add external pullup resistors to the GPIN pins?

No. The GPIN pins are internally pulled up (typical value of 20k) to VL.

11.Can I drive optocouplers from the SPI interface pins?

Yes. The MAX3420E outputs have enough drive current to drive optocoupler LEDs through series resistors. Consult the data sheet for exact drive specs. The output buffers were designed with opto-isolation in mind, since the MAX3420E SPI interface is uniquely suited to electrically