Maxim MAX3420E manual Programming Questions

isolating USB.

12.What is the purpose of the VBCOMP pin? Does it power the MAX3420E?

No. The VBCOMP pin does not power anything in the MAX3420E. It goes only to an internal comparator to detect the presence of VBUS.

4.Programming Questions

1.How does my firmware talk to the MAX3420E?

The MAX3420E has a set of 21 registers that are accessed by its slave SPI interface. The SPI master first sends a command byte that sets the register address and direction, and then transfers one or more data bytes.

2.How do I program the MAX3420E to handle USB enumeration?

As a peripheral, the MAX3420E device needs only to respond to requests from the host (usually a PC).

3.How do I program a BULK IN transfer?

When you have data ready to send to the host, load an IN FIFO, then write the byte count register for the particular endpoint. Since the IN FIFOs are 64 bytes in length, up to 64 bytes can be loaded at a time. When finished loading the data, write the IN endpoint BYTECOUNT register with the number of bytes loaded into the IN FIFO. Writing the byte count register "arms" the endpoint for USB transfer. The MAX3420E does the rest. The next IN request to its device address and the armed endpoint sends the FIFO data to the host.

4.What if a USB IN request comes in while firmware is loading the IN FIFO?

The MAX3420E takes care of this. It automatically answers an IN request to an "unarmed" IN FIFO with a NAK (Negative Acknowledge) handshake. This handshake instructs the USB host that the endpoint is busy, and that the host should try later with another IN request.

5.How do I know when to load an IN FIFO?

The MAX3420E provides interrupt request bits for the IN endpoints called IN3BAVIRQ, IN2BAVIRQ, and IN0BAVIRQ, where "BAV" indicates "Buffer Available". The MAX3420E logic sets an IN endpoint BAVIRQ bit after a device reset, or when IN FIFO data has been successfully transferred and acknowledged by the host. At power-on, the BAVIRQ bits are set to indicate that the IN FIFOS are initially available for loading. These are the only register bits that are set to 1 by a reset—all the rest are set to 0.

6.What if there is a USB transfer error? Do I need to write code to handle the error condition?

No. The MAX3420E manages this for you. If the MAX3420E receives an error condition back from the host, it automatically resends the same data when the host retries the IN transfer. The MAX3420E also automatically handles other error checking such as data toggles. Some possible USB errors (such as a user unplugging the cable in the middle of a data transfer) need to be handled by firmware.

7.How do I program a BULK OUT transfer?

When the host sends OUT data, the MAX3420E stores the bytes in an OUT endpoint FIFO. After the transfer is complete and verified to be error-free, the MAX3420E asserts a "DAV" (Data Available) interrupt request bit for the particular endpoint. This alerts the SPI controller to read the FIFO bytes. The SPI controller first reads an OUT FIFO byte-count register to determine how many bytes in the 64 byte FIFO are valid. It then reads that number of bytes by repeated reads to the OUTFIFO register. Finally, the SPI controller clears the OUT DAV IRQ bit (by writing 1 to it) to "rearm" the endpoint for another OUT transfer.

8.How about INTERRUPT transfers?

Interrupt transfers are programmed identically to BULK transfers. They differ only in how they are described in the device descriptors sent back to the host during enumeration.