HP DL585 - - G2 manual Direct Connect I/O Architecture

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The last two digits, ZZ, indicate the relative performance within the series. Higher numbers indicate higher performance.

In addition, the model number can include a suffix designator to indicate a non-standard power level. HE designates a lower power version, and SE a higher power version. For example, Model 2220, Model 2220 HE, and Model 2220 SE all offer equivalent performance, but differ in power consumption.

The AMD website includes a quick reference guide3 that details each processor part number by socket, revision (stepping), core frequency, manufacturing process (45 nm, 65 nm, or 90 nm), HyperTransport frequency, and wattage.

Direct Connect I/O Architecture

The AMD Direct Connect I/O Architecture replaces the traditional front side bus with point-to-point HyperTransport Technology links and an integrated memory controller connected to dedicated memory banks for each processor.

Integrated memory controller and dedicated memory banks

Each AMD Opteron processor contains an integrated dual-channel SDRAM memory controller that is directly connected to dedicated memory banks. Integrating the controller into the processor means that memory performance can scale linearly based on the number of processors in a multi- processor system. For example, in a multi-processor system, the integrated memory controller allows for multiple memory requests in parallel, thereby increasing the effective memory bandwidth and decreasing average memory latency.

The memory controller operates at a frequency independent of—and usually slower than—the processor core. It has a 128-bit interface that is capable of supporting up to eight DDR2 DIMMs. With four DDR2-800 DIMMs per channel, the memory bandwidth is up to 12.8 GB/s. The 128-bit interface can be divided into two independent 64-bit memory channels for memory controller utilization and better memory performance.

3http://www.amdcompare.com/us-en/AMD Opteron/

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Contents AMD processor roadmap for industry Standard servers Introduction AbstractX86 architecture Bit operationsAMD64 technology Naming conventions Integrated memory controller and dedicated memory banks Direct Connect I/O ArchitectureHyperTransport Technology Multi-core technologies Dual-core Revision F processors Quad-Core AMD Opteron processors Page Page Six-Core AMD Opteron processors Page Conclusion Future AMD Opteron processorsSoftware licensing Call to action For more information