HP DL585 - - G2 manual Multi-core technologies

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Multi-core technologies

In the past, the most common way to improve processor performance was to increase core frequency and/or cache size. However, both of these solutions increase power consumption (and heat generation) and have other limitations. Alternatively, higher performance can be achieved by using multiple execution cores per processor. Multi-core processors run applications more efficiently and allow multi-threaded software to achieve higher performance, while maintaining a similar power budget to single-core processors. Also, multi-core processors are increasingly attractive with reductions in the manufacturing process (for example, from 90 nm to 65 nm to 45 nm). This is because smaller cores require less power, which permits more cores to be built into a single processor.

AMD introduced its first dual-core AMD64 processor in 2005; it was manufactured using a 90 nm process. The AMD Opteron processor is essentially divided into two parts: execution and communications, with a system request interface and crossbar switch linking these two parts (see Figure 2). The crossbar switch architecture enabled AMD Opteron processors to transition easily from single-core to dual-core processors without fundamental design changes.

Each execution core includes a 64-KB/64-KB data/instruction L1 cache and a 1-MB L2 cache. The system request interface manages and prioritizes the processor requests to the crossbar switch. The crossbar switch connects both processor cores directly to communications: I/O (through HyperTransport links) and the integrated memory controller. The memory controller and the HyperTransport links remain the same as in a single core system.

Figure 2. The Socket F (1207) and Socket AM2 designs support dual-core AMD Revision F processors.

The primary difference between the processors designed for single, dual, or multi-core systems is in the way the processor uses the HyperTransport link(s). In the 1000 series AMD Opteron processors, the single HyperTransport link can only connect to I/O in a non-coherent link. This means that the 1000 series processors are limited to single-processor systems. In the 2000 series, one of three HyperTransport links can connect to one other AMD Opteron processor in a coherent link. The

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Contents AMD processor roadmap for industry Standard servers Bit operations AbstractIntroduction X86 architectureAMD64 technology Naming conventions Integrated memory controller and dedicated memory banks Direct Connect I/O ArchitectureHyperTransport Technology Multi-core technologies Dual-core Revision F processors Quad-Core AMD Opteron processors Page Page Six-Core AMD Opteron processors Page Software licensing Future AMD Opteron processorsConclusion Call to action For more information