MSI MS-91E2 manual PAIR3 PAIR2 PAIR1 CFG3 CFG2 CFG1

Page 17

MS-91E2

Boolean table for CPLD behavior of Bypass/PassThrough/WDT function

LAN1-2

PAIR_3

PAIR_2

PAIR_1

CFG_3

CFG_2

CFG_1

 

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

ON

PassTru

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

PassTru

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDT

Reset

 

 

 

 

 

 

 

 

0

0

0

0

0

1

ON

PassTru

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

PassTru

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDT

ByPass

 

 

 

 

 

 

 

 

0

0

0

0

1

0

ON

PassTru

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

ByPass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDT

Reset

 

 

 

 

 

 

 

 

0

0

0

0

1

1

ON

PassTru

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

ByPass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDT

ByPass

 

 

 

 

 

 

 

 

0

0

0

1

0

0

ON

ByPass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

PassTru

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDT

Reset

 

 

 

 

 

 

 

 

0

0

0

1

0

1

ON

ByPass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

PassTru

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDT

ByPass

 

 

 

 

 

 

 

 

0

0

0

1

1

0

ON

ByPass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

ByPass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDT

Reset

 

 

 

 

 

 

 

 

0

0

0

1

1

1

ON

ByPass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OFF

ByPass

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDT

ByPass

 

 

 

 

 

 

 

 

Page 16 Page 18
Image 17
Page 16 Page 18
Contents MS-91E2 Trademarks Copyright NoticeRevision History Technical SupportSafety Instructions FCC-B Radio Frequency Interference Statement OIR LA Notice D’INSTALLATION Avant DE Raccorder AU ReseauWeee Statement EnglishEspañol Türkçe Contents Overview Processor ConnectorChipset MemoryMainboard Layout Watch Dog Timer Setting Setup procedures Page Mov Al, 0aah Out Dx, al Programming Sequence LAN Bypass Function Programming GuideLAN Bypass Function Programming Guide Page PAIR3 PAIR2 PAIR1 CFG3 CFG2 CFG1 LAN3-4 Hardware Setup CPUFAN2 Quick Components GuideCPU Central Processing Unit Introduction to LGA 1366 CPUAlignment Key CPU & Cooler InstallationPage Memory Installing Memory ModulesPower Supply System Power Connector JPWR3CPU Power Connector JPWR1, JPWR2 Connector Fan Power Connector CPUFAN1~2, SYSFAN1~3Mouse/Keyboard Connector JP1 LAN Port JLAN1, JLAN2 Serial ATA Connector SATA1~SATA6VGA Port JVGA1 USB 2.0 Bracket Serial Port Connector JCOM1Front USB Connector JUSB1, JUSB2 Serial Port/ LAN LED/ Status LED Connector J1 SMBus Connector J3Front Panel Connector J4 TPM Module Connector JTPM1 Gpio Connector J6Jumper Clear Cmos Jumper JBAT1Slot PCI Peripheral Component Interconnect Express SlotCF Socket PCI Express Resource Limitation Installed Empty Bios Setup Entering Setup Press DEL or F2 to enter SetupGetting Help Control KeysMain Menu Sub-MenuMenu Bar Main BootAdvanced ChipsetSystem Time Main Bios Information, Memory Information, Access LevelSystem Date Advanced Launch PXE OpROM, Launch Storage OpROM Acpi SettingsCPU Configuration Intel Virtualization Technology Resume On RTC AlarmSuper IO Configuration Sata Configuration Sata ModeMonitor JCOM1 Configuration, COM2 Configuration Serial PortDevice Settings Serial Port Console Redirection SYS0 FAN Mode SettingCPU1 Fan Setting, CPU2 Fan Setting Legacy OS Redirection Resolution Console Redirection Settings Terminal TypeBits per second, Data Bits, Parity, Stop Bits Flow ControlChipset North Bridge Interrupt Remapping IntelR VT for Directed I/O Configuration IntelR VT-dCoherency Support ATS SupportQPI Link QPI Frequency Select LAN Watch Dog Time Out Event South Bridge Restore AC Power LossLAN State at Power On, LAN State at Power Off Boot Option Priorities Boot Setup Prompt TimeoutBootup NumLock State User Password Security Administrator PasswordPending TPM Operation Trusted Computing TPM SupportTPM State Discard Changes and Reset Save & Exit Save Changes and ResetSave Changes Discard Changes
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