Introduction to SHARC Processors
•An SDRAM controller that provides an interface to as many as four separate banks of
•Up to a maximum of 5M bits of
•Input/output processor (IOP) with integrated direct memory access (DMA) controller, serial peripheral interface (SPI) compati- ble port, and serial ports (SPORTs) for
•A variety of
•JTAG test access port for emulation
Figure 1-1 also shows the three on-chip buses of the ADSP-21472/21475/21479 processors: the PM bus, DM bus, and I/O bus. The PM bus provides access to instructions or data. During a single cycle, these buses let the processor access two data operands from memory, access an instruction (from cache), and perform a DMA transfer. In addi- tion, Figure 1-1 shows the asychronous memory interface available on the ADSP-2147x processors.
Four Generations of SHARC Processors
The SHARC architecture has a long history in the
Getting Started With SHARC Processors |