Performance

Processor Peripherals and Performance

Integration of peripherals continue with serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller, again preserving internal memory space for code and data. The fourth generation processor also incorporates link ports that allow processor-to-processor communica- tion for data movement. Some fourth generation SHARC processors also integrate real-time clock (RTC) and watchdog timer functionality. In addition, a number of fourth generation processors are also pin compati- ble for use with a single hardware platform.

Each SHARC processor provides unique capabilities, while being code compatible with previous generations of SHARC devices, so legacy code is easily ported to the newer products. Table 1-1, Table 1-2, Table 1-3, Table 1-4, and Table 1-5list key SHARC processor specifications. For more information, view the SHARC processor selection table online at the Analog Devices Web site at:

http://www.analog.com/sharc

Processor Peripherals and Performance

SHARC processors represent a class of devices that combine an extremely capable single-instruction, multiple-data (SIMD) processor engine with features like core timers, general-purpose timers, UARTs, and SPI ports.

In addition to advanced peripherals, SHARC processors use a software programmable, on-chip phase lock loop (PLL) that allows software control during runtime of core and peripheral clock of the SHARC processors.

Real-time signal processing tasks are I/O and computationally intensive. In addition to high speed math units and single cycle instruction

1-8	Getting Started With SHARC Processors

82-003536-01 specifications

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