Analog Devices ADSP-BF538F manuals
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Analog Devices ADSP-BF538F System Manual
101 pages 3.12 Mb
3 Regulatory Compliance 5 CONTENTS9 PREFACE10 L17 L21 L a [71 SCHEMATICADSP-BF538F EZ-KIT LITETITLE 72 RTCDSP 73 DSP POWER74 (8M x 8 x 4 banks) x 2 chipsSDRAM AND FLASH10-15-2007_13:17 4 13 Memory Map DEVICESTART END BANK SDRAM Bank 0 64MB SDRAM 64 MB SDRAM 4 MB FLASH (2M x 16)0x2000 0000 ASYNC Memory Bank 0 ASYNC Memory Bank 1 ASYNC Memory Bank 2 ASYNC Memory Bank 3 0x200F FFFF 0x2010 0000 0x2020 0000 0x201F FFFF 0x202F FFFF 0x203F FFFF0x2030 0000 1 MB FLASHSW6: FLASH Enable Switch SW14: FCE Enable Switch ADC LEFT 75 ADC AND AUDIO INLABEL "LINE IN" ADC 10-15-2007_13:17 5 13 ADC RIGHTSW7: Audio Selection Switch DAC LEFT DAC RIGHT 76 DACDAC AND AUDIO OUT 77 CANCAN 78 PUSH BUTTONS, LEDS AND BOOT MODE4-29-2008_15:55 8 13LABEL "PB2" LABEL "PB4" LABEL "PB3" SW5: Push Button Enable Switch SW3: Boot Mode Select Switch 1BMODE1 2BOOT MODEBMODE0 79 DSP CORE VOLTAGE & CURRENTELVIS Voltage Selection Jumper ELVIS INTERFACE13910-15-2007_13:17NI ELVIS ID 33 (0010 0001) ELVIS CONNECTOR PFI DSP IO CURRENTSW8: Function Generator Switch SW1: Oscilloscope Select Switch PH: 1-800-ANALOGDWhen designing your JTAG interface please refer to the 131010-15-2007_13:17 80 DSP JTAG HEADEREngineer to Engineer Note EE-68 which can be found at EXPANSION INTERFACE & JTAGhttp://www.analog.com All USB interface circuitry is considered proprietary and has been omitted from this schematic. EXPANSION INTERFACE (TYPE B) 81 (UART 0)SERIAL PORT STAMP CONNECTORS SPI TIMERS SPORT 1 PPI SPORT 0 TWI UART 82 MISC CONNECTORSSPI 1 SPI 2 UART 1 UART 2 TWI1 83 POWER131310-15-2007_13:173.3V@3A LABEL "VDDINT" LABEL "GND" LABEL "3.3V" LABEL "5V" ADSP-BF538F EZ-KIT Lite Evaluation System Manual I-1 84 INDEX
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