Epson RX-8581NB manuals
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2 In pursuit of "Saving" Technology ,Epson electronic device"Saving Epson IS energy savings •The material is subject to change without notice 3 7.1. DC characteristics4 PageMQ372-02 5 RX - 8581 SARX - 8581 JE RX - 8581 NB Signal I/O name This is the serial clock input pin for I2C Bus communications This pin's signal is used for input and output of address, data, and ACK bits SDA I/O synchronized with the serial clock used for I2C communications pull-upresistance relative to the signal line capacity This is the C-MOSoutput pin with output control provided via the FOE pin When FOE = "H" (high level), this pin outputs a 32.768-kHzsignal When output is stopped, the FOUT pin = "L" (low level) This is an input pin used to control the output mode of the FOUT pin FOE FOUT pin is stopped /INT signals. This pin is an open drain pin This pin is connected to a positive power supply (VDD) GND This pin is connected to a ground This pin is not connected to the internal IC N.C Leave N.C. pins open or connect them to GND or VDD 22) are interconnected via the internal frame 6 ItemSymbol Condition Rating Unit Min Typ Max 7 SCLSDA 8 8.1. Overview of Functions 1) Clock functions2)Fixed-cycleinterrupt generation function 3)Time update interrupt function 4)Alarm interrupt function 5)32.768-kHzclock output 6) Interface with CPU 9 Address10 8.2.2. Control register (Reg F)STOP RESET 1) UIE (Update Interrupt Enable) bit When a time update interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z) Write/Read When a time update interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) 2)TIE (Timer Interrupt Enable) bit When a fixed-cycletimer interrupt event occurs, an interrupt signal is not When a fixed-cycletimer interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) 3)AIE (Alarm Interrupt Enable) bit When an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z) When an alarm interrupt event occurs, an interrupt signal is generated 11 4) STOP bitWriting a "0" to this bit cancels stop status (restarts operations) STOP Description [Normal operation mode] function. Also, when "1" is written to the STOP bit, it cancels stop status for the fixed-cycletimer function [Operation stop mode] Stops updating of year, month, date, day, hour, minute, and second values and partially stops the fixed-cycletimer function (Stop 1) Stops updating of year, month, date, day, hour, minute, and second values • This stops all clock and calendar update operations Once this occurs, no more time update interrupt events or alarm interrupt events occur (Stop 2) Partially stops the fixed-cycletimer function • If the fixed-cycletimer's source clock settings include an update setting of 64 Hz, 1 Hz, or "Minute", the fixed-cycletimer function does not operate when the fixed-cycle timer's source clock setting is 4096 Hz 5) RESET bit RESET 12 8.2.3. Flag register (Reg-E)Flag register ∗ 1) ∗ 2) 1)UF (Update Flag) bit 2)TF (Timer Flag) bit 3)AF (Alarm Flag) bit 4)VLF (Voltage Low Flag) bit This bit's value is "1" after powering up from 0 VLF The VLF bit is cleared to zero to prepare for the next status detection Write This bit is invalid after a "1" has been written to it Data loss is not detected Read Data loss is detected All registers must be initialized (This setting is retained until a "zero" is written to this bit.) 13 8.2.4. Extension register (Reg-D)WADA USEL TSEL1 ∗ 3) 1) TEST bit TEST Normal operation mode Setting prohibited (manufacturer's test bit) 2) WADA (Week Alarm/Day Alarm) bit 3)USEL (Update Interrupt Select) bit 4)TE (Timer Enable) bit 5)TSEL0,1 (Timer Select 0, 1) bits TSEL0,1 Source clock (bit 1) (bit 0) /Once per 244.14 ∝ s / Once per 15.625 ms "Second" update /Once per second "Minute" update /Once per minute 8.2.5. RAM register (Reg - 7) 16 8.3. Fixed-cycleTimer Interrupt Function8.3.1. Diagram of fixed-cycletimer interrupt function TE bit TIE bit /INT output TF bit When a "1" is written to the TE bit, the When a (4)When the TF bit = "1" its value is retained until it is cleared to zero If the TIE bit = "1" when a If the TIE bit = "0" when a ∗/INT is again set low when the next interrupt event occurs When a "0" is written to the TE bit, the When /INT = low, the When /INT = low, the /INT pin status changes from low to 17 8.3.2. Related registers for function of time update interruptsTSEL1 TSEL0 interrupts from occurring inadvertently while entering settings When the can be used as a RAM register. In such cases, stop the 1)TSEL0,1 bits (Timer Select 0, 1) TSEL0,1 Auto reset time Effects of STOP tRTN and RESET bits Hz /Once per 244.14 ∝ s 122 ∝ s Write/Read 7.8125 ms 2) Fixed-cycleTimer Control register (Reg - B ∼ C) Address C Address B Timer Counter bit 3) TE (Timer Enable) bit Data Stops fixed-cycletimer interrupt function Starts fixed-cycletimer interrupt function 4) TF (Timer Flag) bit The TF bit is cleared to zero to prepare for the next status detection Fixed-cycletimer interrupt events are not detected Fixed-cycletimer interrupt events are detected (Result is retained until this bit is cleared to zero.) 18 SCL pinSDA pin /INT pin 19 8.4.1. Time update interrupt function diagram(2)When a time update interrupt event occurs, the UF bit value becomes "1 When the UF bit value is "1" its value is retained until it is cleared to zero (4)When a time update interrupt occurs, /INT pin output is low if UIE = "1 If UIE = "0" when a timer update interrupt occurs, the /INT pin status remains ∗/INT pin output goes low again when the next interrupt event occurs 20 8.4.2. Related registers for time update interrupt functions1)USEL (Update Interrupt Select) bit Selects "second update" (once per second) as the timing for generation of interrupt events Selects "minute update" (once per minute) as the timing for generation of 2) UF (Update Flag) bit The UF bit is cleared to zero to prepare for the next status detection Time update interrupt events are not detected Time update interrupt events are detected (The result is retained until this bit is cleared to zero.) 3) UIE (Update Interrupt Enable) bit 1) Does not generate an interrupt signal when a time update interrupt event occurs (/INT remains Hi-Z) 2) Cancels interrupt signal triggered by time update interrupt event (/INT changes from low to Hi-Z) 22 8.5.2. Related registersfrom occurring inadvertently while entering settings 1) WADA (Week Alarm /Day Alarm) bit WADA Sets WEEK as target of alarm function (DAY setting is ignored) Sets DAY as target of alarm function (WEEK setting is ignored) 2) Alarm registers (Reg - 8 to A) ∗1) The register that "1" was set to "AE" bit, doesn't compare alarm (Example) Write 80h (AE = "1") to the WEEK Alarm /DAY Alarm register (Reg - A): As a result, alarm occurs if only an hour and minute accords with alarm data 23 3) AF (Alarm Flag) bitThe AF bit is cleared to zero to prepare for the next status detection Alarm interrupt events are not detected Alarm interrupt events are detected 4) AIE (Alarm Interrupt Enable) bit 1) When an alarm interrupt event occurs, an interrupt signal is not 2) When an alarm interrupt event occurs, the interrupt signal is canceled (/INT status changes from low to Hi-Z) When an alarm interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Zto low) 8.5.2.Examples of alarm settings 1)Example of alarm settings when "Day" has been specified (and WADA bit = "0") Day is specified Reg – A Reg WADA bit = "0 S F T W T M S Alarm Monday through Friday, at 7:00 AM 07 h 80 h ∼ FF h ∗ Minute value is ignored Every Saturday and Sunday, for 30 minutes 30 h each hour ∗ Hour value is ignored Every day, at 6:59 AM 18 h 59 h Χ: Don't care 2)Example of alarm settings when "Day" has been specified (and WADA bit = "1") Reg - A WADA bit = "1 First of each month, at 7:00 AM 15th of each month, for 30 minutes each hour ∗ Hour value is ignored Every day, at 6:59 PM Χ : Don't care 24 8.6. Reading/Writing Data via the I2C Bus Interface25 8.6.3. Starting and stopping I2C bus communications0.95 s ( Max. ) 1) START condition, repeated START condition, and STOP condition (1)START condition The SDA level changes from high to low while SCL is at high level (2)STOP condition (3)Repeated START condition (RESTART condition) 2)Caution points within 0.95 seconds 0.95 seconds or longer 4) When communicating with this RTC module, wait at least 1.3 µs (see the tBUF rule) 61 ∝ s (Min.) 26 8.6.4.Data transfers and acknowledge responses during I2C-BUScommunications1)Data transfers However, the transfer time must be no longer than 0.95 seconds After address Fh, incrementation goes to address 0h 2)Data acknowledge response (ACK signal) 8.6.5. Slave address [1010 Transfer data Read A3 h A2 h Slave address R/W bit 1 (= Read) 0 (= Write) 29 RX-8581SA (SOP - 14 pin)•External dimensions R8581 E 1234A •Recommended soldering RX-8581JE (VSOJ - 20 pin) RX-8581NB (SON - 22 pin) R8564 31 (1) Static electricity(2) Noise (3)Voltage levels of input pins (4) Handling of unused pins 11.2.Notes on packaging (1)Soldering heat resistance (2)Mounting equipment (3) Ultrasonic cleaning (4) Mounting orientation (5) Leakage between pins Fig. 1 : Example GND Pattern Fig. 2 : Reference profile for our evaluation of Soldering heat resistance RX - 8581 SA RX - 8581 JE RX - 8581 NB 32 DistributorAMERICA EPSON ELECTRONICS AMERICA, INC HEADQUARTER 150 River Oaks Parkway, San Jose, CA 95134, U.S.A http://www.eea.epson.com Atlanta Office 3010 Royal Blvd. South, Ste. 170, Alpharetta, GA 30005, U.S.A Boston Office Chicago Office 101 Virginia St., Ste. 290, Crystal Lake, IL 60014, U.S.A El Segundo Office 1960 E. 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