Motorola MPC8260 manuals
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1006 pages 9.94 Mb
5 About This Book Overview 6 PowerPC Processor Core 7 Memory Map System Interface Unit (SIU) 8 Reset 9 External Signals 60x Signals 10 The 60x Bus 11 Clocks and Power Control 12 Memory Controller 14 Secondary (L2) Cache Support IEEE 1149.1 Test Access Port 15 Communications Processor Module Overview 16 Serial Interface with Time-Slot Assigner CPM Multiplexing 17 Baud-Rate Generators (BRGs) Timers SDMA Channels and IDMA Emulation 18 Serial Communications Controllers (SCCs) 19 SCC UART Mode 20 SCC HDLC Mode SCC BISYNC Mode 21 SCC Transparent Mode SCC Ethernet Mode 22 SCC AppleTalk Mode Serial Management Controllers (SMCs) 24 Multi-Channel Controllers (MCCs)Fast Communications Controllers (FCCs) 25 ATM Controller28 Fast Ethernet Controller29 FCC HDLC ControllerFCC Transparent Controller Serial Peripheral Interface (SPI) 30 I2C ControllerParallel I/O Ports 55 About This Book67 Part I71 Chapter 1 89 Chapter 2 PowerPC Processor Core121 Chapter 3 Memory Map135 Part II Conguration and Reset139 Chapter 4 System Interface Unit (SIU)185 Chapter 5 Reset5.1 Reset Causes 188 5.2 Reset Status Register (RSR)Table 5-3 describes RSR elds.Figure 5-1. Reset Status Register (RSR) Table 5-3. RSR Field Descriptions MOTOROLA Chapter 5. Reset 5-5 189 5.3 Reset Mode Register (RMR)Table 5-4 describes RMR elds. The reset mode register (RMR), shown in Figure 5-2, is memory-mapped into the SIU register map. Figure 5-2. Reset Mode Register (RMR) Table 5-4. RMR Field Descriptions Table 5-3. RSR Field Descriptions (Continued) 190 5.4 Reset Conguration197 Part III The Hardware Interface203 Chapter 6 External Signals215 Chapter 7 60x Signals233 Chapter 8 The 60x Bus267 Chapter 9 Clocks and Power Control277 Chapter 10 Memory ControllerMOTOROLA Chapter 10. Memory Controller 10-3 Figure 10-1. Dual-Bus Architecture 279 10.1 Features281 10.2 Basic Architecture289 10.3 Register DescriptionsTable 10-2 lists registers used to control the 60x bus memory controller.Table 10-2. 60x Bus Memory Controller Registers Internal 10-14 MPC8260 PowerQUICC II Users Manual MOTOROLA 290 10.3.1 Base Registers (BRx)Table 10-3 describes BRx elds. 292 10.3.2 Option Registers (ORx)297 10.3.3 60x SDRAM Mode Register (PSDMR)Table 10-7 describes PSMDR elds. LSMDR elds are described in Table 10-8. 300 10.3.4 Local Bus SDRAM Mode Register (LSDMR)302 10.3.5 Machine A/B/C Mode Registers (MxMR)100 Figure 10-11. Machine x Mode Registers (MxMR) Table 10-8. LSDMR Field Descriptions (Continued)MOTOROLA Chapter 10. Memory Controller 10-27 303 Table 10-9 describes MxMR bits.Table 10-9. Machine x Mode Registers (MxMR) 10-28 MPC8260 PowerQUICC II Users Manual MOTOROLA 304 10.3.6 Memory Data Register (MDR)Table 10-9. Machine x Mode Registers (MxMR) (Continued)MOTOROLA Chapter 10. Memory Controller 10-29 Table 10-10 describes MDR elds. 305 10.3.7 Memory Address Register (MAR)Figure 10-13. Memory Address Register (MAR) The memory address register (MAR) is shown in Figure 10-13.Figure 10-12. Memory Data Register (MDR) Table 10-10. MDR Field Descriptions10-30 MPC8260 PowerQUICC II Users Manual MOTOROLA Table 10-11 describes MAR elds. 306 10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)The local bus assigned UPM refresh timer register (LURT) is shown in Figure 10-15. The 60x bus assigned UPM refresh timer register (PURT) is shown in Figure 10-14. Table 10-12 describes PURT elds. 10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)Table 10-11. MAR Field Description Figure 10-15. Local Bus-Assigned UPM Refresh Timer (LURT)MOTOROLA Chapter 10. Memory Controller 10-31 Table 10-13 describes LURT elds. 307 10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)Table 10-14 describes PSRT elds. The 60x bus assigned SDRAM refresh timer register (PSRT) is shown in Figure 10-16. Table 10-13. Local Bus-Assigned UPM Refresh Timer (LURT) 10-32 MPC8260 PowerQUICC II Users Manual MOTOROLA 308 10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)The local bus-assigned SDRAM refresh timer register (LSRT) is shown in Figure 10-17. Table 10-16 describes MPTPR elds. Table 10-15 describes LSRT elds. 10.3.12 Memory Refresh Timer Prescaler Register (MPTPR)Figure 10-18 shows the memory refresh timer prescaler register (MPTPR). Figure 10-17. Local Bus-Assigned SDRAM Refresh Timer (LSRT) Table 10-15. LSRT Field Descriptions Figure 10-18. Memory Refresh Timer Prescaler Register (MPTPR) Table 10-16. MPTPR Field Descriptions 10.3.13 60x Bus Error Status and Control Registers (TESCRx) 10.3.14 Local Bus Error Status and Control Registers (L_TESCRx) 309 10.4 SDRAM Machine10-34 MPC8260 PowerQUICC II Users Manual MOTOROLA 310 Figure 10-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)311 10.4.1 Supported SDRAM Congurations10.4.2 SDRAM Power-On Initialization 10.4.3 JEDEC-Standard SDRAM Interface Commands 312 10.4.4 Page-Mode Support and Pipeline Accesses10.4.5 Bank Interleaving 313 10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA)314 10.4.6 SDRAM Device-Specic Parameters10.4.6.1 Precharge-to-Activate Interval MOTOROLA Chapter 10. Memory Controller 10-39 Figure 10-20. PRETOACT = 2 (2 Clock Cycles) 315 10.4.6.2 Activate to Read/Write Interval This parameter, controlled by P/LSDMR[ACTTORW], denes the earliest timing forREAD/WRITE command after an ACTIVATE command. Figure 10-21. ACTTORW = 2 (2 Clock Cycles)10-40 MPC8260 PowerQUICC II Users Manual MOTOROLA 316 10.4.6.3 Column Address to First Data OutCAS Latency Figure 10-22. CL = 2 (2 Clock Cycles) 10.4.6.4 Last Data Out to Precharge This parameter, controlled by P/LSDMR[LDOTOPRE], denes the earliest timing for thePRECHARGE command after the last data was read from the SDRAM. It is always related to the CL parameter.Figure 10-23. LDOTOPRE = 2 (-2 Clock Cycles)MOTOROLA Chapter 10. Memory Controller 10-41 317 10.4.6.5 Last Data In to PrechargeWrite Recovery Figure 10-24. WRC = 2 (2 Clock Cycles) 10.4.6.6 Refresh Recovery Interval (RFRC)This parameter, controlled by P/LSDMR[RFRC], denes the earliest timing for anACTIVATE command after a REFRESH command. Figure 10-25. RFRC = 4 (6 Clock Cycles) 10.4.6.7 External Address Multiplexing Signal 318 10.4.6.8 External Address and Command Buffers (BUFCMD)10.4.7 SDRAM Interface TimingMOTOROLA Chapter 10. Memory Controller 10-43 319 Figure 10-28. SDRAM Single-Beat Read, Page Closed, CL = 3Figure 10-29. SDRAM Single-Beat Read, Page Hit, CL = 3 Figure 10-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 310-44 MPC8260 PowerQUICC II Users Manual MOTOROLA 320 Figure 10-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3Figure 10-32. SDRAM Single-Beat Write, Page Hit Figure 10-33. SDRAM Three-Beat Burst Write, Page ClosedMOTOROLA Chapter 10. Memory Controller 10-45 321 Figure 10-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3Figure 10-35. SDRAM Write-after-Write Pipelined, Page Hit Figure 10-36. SDRAM Read-after-Write Pipelined, Page Hit 322 10.4.8 SDRAM Read/Write Transactions10.4.9 SDRAM MODE-SET Command Timing 323 10.4.10 SDRAM Refresh10.4.11 SDRAM Refresh Timing 324 10.4.12 SDRAM Conguration Examples10.4.12.1 SDRAM Conguration Example (Page-Based Interleaving) 326 10.4.13 SDRAM Conguration Example (Bank-Based Interleaving)327 10.5 General-Purpose Chip-Select Machine (GPCM)338 10.6 User-Programmable Machines (UPMs)357 10.7 Memory System Interface Example Using UPM376 10.8 Handling Devices with Slow or Variable Access Times 10.8.1 Hierarchical Bus Interface Example 10.8.2 Slow Devices Example 377 10.9 External Master Support (60x-Compatible Mode)383 Chapter 11 Secondary (L2) Cache Support393 Chapter 12 IEEE 1149.1 Test Access Port423 Part IV Communications Processor Module 431 Chapter 13 Communications Processor Module 491 Chapter 15 CPM Multiplexing509 Chapter 16 Baud-Rate Generators (BRGs)515 Chapter 17 TimersFigure 17-1. Timer Block Diagram Pin assignments for TINx, TGATEx, and TOUTx are described in Section 35.5, Ports Tables. 516 17.1 Features17.2 General-Purpose Timer Units 525 Chapter 18 SDMA Channels and IDMA Emulation557 Chapter 19 Serial Communications Controllers (SCCs)585 Chapter 20 SCC UART Mode609 Chapter 21 SCC HDLC Mode633 Chapter 22 SCC BISYNC Mode653 Chapter 23 SCC Transparent Mode669 Chapter 24 SCC Ethernet Mode693 Chapter 25 SCC AppleTalk Mode697 Chapter 26 Serial Management Controllers (SMCs)731 Chapter 27 Multi-Channel Controllers (MCCs)759 Chapter 28 Fast Communications Controllers (FCCs)781 Chapter 29 ATM Controller875 Chapter 30 Fast Ethernet Controller903 Chapter 31 FCC HDLC Controller921 Chapter 32 FCC Transparent Controller 922 32.1 Features32.2 Transparent Channel Operation 32.3 Achieving Synchronization in Transparent Mode 925 Chapter 33 Serial Peripheral Interface (SPI)943 Chapter 34 I2C Controller957 Chapter 35 Parallel I/O Ports35.1 Features 958 35.2 Port Registers 35.2.1 Port Open-Drain Registers (PODRAPODRD) 35.2.2 Port Data Registers (PDATAPDATD)MOTOROLA Chapter 35. Parallel I/O Ports 35-3 959 35.2.3 Port Data Direction Registers (PDIRAPDIRD)Table 35-2 describes PDIR elds. The port data direction register(PDIR), shown in Figure 35-3, is cleared at system reset.Figure 35-2. Port Data Registers (PDATAPDATD) Figure 35-3. Port Data Direction Register (PDIR) Table 35-2. PDIR Field Descriptions 35-4 MPC8260 PowerQUICC II Users Manual MOTOROLA 960 35.2.4 Port Pin Assignment Register (PPAR)The port pin assignment register (PPAR) is cleared at system reset. Table 35-2 describes PPARx elds. 35.2.5 Port Special Options Registers AD (PSORAPSORD)Figure 35-5 shows the port special options registers (PSORx).Figure 35-4. Port Pin Assignment Register (PPARAPPARD) Table 35-3. PPAR Field Descriptions MOTOROLA Chapter 35. Parallel I/O Ports 35-5 961 NOTEFigure 35-5. Special Options Registers (PSORAPOSRD) Table 35-4. PSORx Field Descriptions 35-6 MPC8260 PowerQUICC II Users Manual MOTOROLA 962 35.3 Port Block DiagramFigure 35-6 shows the functional block diagram. Figure 35-6. Port Functional Operation 35.4 Port Pins FunctionsEach pin can operate as a general purpose I/O pin or as a dedicated input or output pin. 35.4.1 General Purpose I/O Pins 35.4.2 Dedicated Pins 963 35.5 Ports Tables975 35.6 Interrupts from Port CTable 35-8. Port D Dedicated Pin Assignment (PPARD = 1) (Continued) MOTOROLA Appendix A. Register Quick Reference Guide A-1 977 Appendix A Register Quick Reference GuideThis section provides a brief guide to the core registers. Table A-2 lists SPRs dened by the PowerPC architecture implemented on the MPC8260. A.1 PowerPC RegistersUser RegistersTable A-1. User-Level PowerPC Registers (Non-SPRs) Table A-2. User-Level PowerPC SPRs A-2 MPC8260 PowerQUICC II Users Manual MOTOROLA Appendixes 978 A.2 PowerPC RegistersSupervisor RegistersTable A-4 lists supervisor-level SPRs defined by the PowerPC architecture. Table A-3. Supervisor-Level PowerPC Registers (Non-SPR) Table A-4. Supervisor-Level PowerPC SPRs MOTOROLA Appendix A. Register Quick Reference Guide A-3 Appendixes 979 A.3 MPC8260-Specic SPRs1005 Attention!
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