Motorola MPC8260 10.5.1.3 Relaxed Timing

MOTOROLA Chapter 10. Memory Controller 10-55
Part III. The Hardware Interface
Figure 10-45. GPCM Memory Device Basic Timing (ACS ¹ 00, CSNT = 1, TRLX = 0)
10.5.1.3 Relaxed Timing
ORx[TRLX] is provided for memory systems that require more relaxed timing between
signals. When TRLX = 1 and ACS ¹ 00, an additional cycle between the address and
strobes is inserted by the MPC8260 memory controller. See Figure 10-46 and
Figure 10-47.
Figure 10-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)
Clock
Address
PSDVAL
CS
WE
Data
CSNT = 1
ACS = 11
ACS = 10
Clock
Address
PSDVAL
CS
R/W
WE
OE
Data
ACS = 10
ACS = 11