Motorola MPC8260 - page 34

xxxiv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
ILLUSTRATIONS
Figure
Number Title Page
Number
4-20 SIU External Interrupt Control Register (SIEXR)...................................................4-25
4-21 Bus Configuration Register (BCR)..........................................................................4-26
4-22 PPC_ACR................................................................................................................ 4-28
4-23 PPC_ALRH............................................................................................................. 4-29
4-24 PPC_AALRL........................................................................................................... 4-29
4-25 LCL_ACR................................................................................................................4-29
4-26 LCL_ALRH............................................................................................................. 4-30
4-27 LCL_ALRL............................................................................................................. 4-31
4-28 SIU Model Configuration Register (SIUMCR).......................................................4-31
4-29 Internal Memory Map Register (IMMR).................................................................4-34
4-30 System Protection Control Register (SYPCCR)......................................................4-35
4-31 The 60x Bus Transfer Error Status and Control Register 1 (TESCR1)...................4-36
4-32 60x Bus Transfer Error Status and Control Register 2 (TESCR2).......................... 4-37
4-33 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1).................. 4-38
4-34 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2).................. 4-39
4-35 Time Counter Status and Control Register (TMCNTSC)....................................... 4-40
4-36 Time Counter Register (TCMCNT)........................................................................ 4-41
4-37 Time Counter Alarm Register (TMCNTAL).......................................................... 4-42
4-38 Periodic Interrupt Status and Control Register (PISCR)......................................... 4-42
4-39 Periodic interrupt Timer Count Register (PITC)..................................................... 4-43
4-40 Periodic Interrupt Timer Register (PITR)................................................................4-44
5-1 Reset Status Register (RSR)...................................................................................... 5-4
5-2 Reset Mode Register (RMR)..................................................................................... 5-5
5-3 Hard Reset Configuration Word................................................................................ 5-8
5-4 Single Chip with Default Configuration..................................................................5-10
5-5 Configuring a Single Chip from EPROM............................................................... 5-10
5-6 Configuring Multiple Chips.....................................................................................5-11
6-1 MPC8260 External Signals........................................................................................6-2
7-1 PowerPC Signal Groupings....................................................................................... 7-2
8-1 Single MPC8260 Bus Mode...................................................................................... 8-3
8-2 60x-Compatible Bus Mode........................................................................................8-4
8-3 Basic Transfer Protocol............................................................................................. 8-5
8-4 Address Bus Arbitration with External Bus Master.................................................. 8-9
8-5 Address Pipelining...................................................................................................8-10
8-6 Interface to Different Port Size Devices.................................................................. 8-17
8-7 Retry Cycle.............................................................................................................. 8-24
8-8 Single-Beat and Burst Data Transfers..................................................................... 8-28
8-9 128-Bit Extended Transfer to 32-Bit Port Size........................................................8-29
8-10 Burst Transfer to 32-Bit Port Size........................................................................... 8-30
8-11 Data Tenure Terminated by Assertion of TEA........................................................8-31
8-12 MEI Cache Coherency ProtocolÑState Diagram (WIM = 001).............................8-32
9-1 System PLL Block Diagram...................................................................................... 9-5
9-2 PLL Filtering Circuit................................................................................................. 9-8