Main
Page
Page
Page
About This Book
Overview
PowerPC Processor Core
Memory Map
System Interface Unit (SIU)
Reset
External Signals
60x Signals
The 60x Bus
Clocks and Power Control
Memory Controller
Page
Secondary (L2) Cache Support
IEEE 1149.1 Test Access Port
Communications Processor Module Overview
Serial Interface with Time-Slot Assigner
CPM Multiplexing
Baud-Rate Generators (BRGs)
Timers
SDMA Channels and IDMA Emulation
Serial Communications Controllers (SCCs)
SCC UART Mode
SCC HDLC Mode
SCC BISYNC Mode
SCC Transparent Mode
SCC Ethernet Mode
SCC AppleTalk Mode
Serial Management Controllers (SMCs)
Page
Multi-Channel Controllers (MCCs)
Fast Communications Controllers (FCCs)
ATM Controller
Page
Page
Fast Ethernet Controller
FCC HDLC Controller
FCC Transparent Controller
Serial Peripheral Interface (SPI)
I2C Controller
Parallel I/O Ports
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About This Book
Before Using this ManualImportant Note
Audience
Organization
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MOTOROLA About This Book lxi
Table i. Acronyms and Abbreviated Terms
lxii MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA About This Book lxiii
lxiv MPC8260 PowerQUICC II Users Manual MOTOROLA
PowerPC Architecture Terminology Conventions
Table ii. Terminology Conventions
MOTOROLA About This Book lxv
Table iii describes instruction eld notation conventions used in this manual.
Table iii. Instruction Field Conventions
Page
Part I
Page
MOTOROLA Part I. Overview Part I-lxix
Table iv. Acronyms and Abbreviated Terms (Continued)
Page
Chapter 1
1.1 Features
Page
Page
1.2 MPC8260s Architecture Overview
1.2.1 MPC603e Core
1.2.2 System Interface Unit (SIU)
1.2.3 Communications Processor Module (CPM)
1.3 Software Compatibility Issues
1.3.1 Signals
Figure 1-2. MPC8260 External Signals
P O W E R Q U I
II
1.4 Differences between MPC860 and MPC8260
1.5 Serial Protocol Table
1.6 MPC8260 Congurations
1.6.1 Pin Congurations
1.6.2 Serial Performance
1.7 MPC8260 Application Examples
1.7.1 Examples of Communication Systems
1.7.1.1 Remote Access Server
1.7.1.2 Regional Ofce Router
1.7.1.3 LAN-to-WAN Bridge Router
1-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
1.7.1.4 Cellular Base Station
Figure 1-6 shows a cellular base station conguration.
Figure 1-6. Cellular Base Station Configuration
1.7.1.5 Telecommunications Switch Controller
Figure 1-7 shows a telecommunications switch controller conguration.
1.7.1.6 SONET Transmission Controller
1.7.2 Bus Congurations
1.7.2.1 Basic System
1-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 1-9. Basic System Configuration
1.7.2.2 High-Performance Communication
Figure 1-10 shows a high-performance communication conguration.
Figure 1-10. High-Performance Communication
1.7.2.3 High-Performance System Microprocessor
Page
Chapter 2 PowerPC Processor Core
2.1 Overview
2-2 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 2-1. MPC8260 Integrated Processor Core Block Diagram
Instruction Unit
2.2 PowerPC Processor Core Features
Page
2.2.1 Instruction Unit
2.2.2 Instruction Queue and Dispatch Unit
2.2.3 Branch Processing Unit (BPU)
2.2.4 Independent Execution Units
2.2.4.1 Integer Unit (IU)
2.2.4.2 Load/Store Unit (LSU)
2.2.4.3 System Register Unit (SRU)
2.2.5 Completion Unit
2.2.6 Memory Subsystem Support
2.2.6.1 Memory Management Units (MMUs)
2.3 Programming Model
2.3.1 Register Set
2.3.1.1 PowerPC Register Set
2-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 2-2. MPC8260 Programming ModelRegisters
Exception Handling Registers
Memory Management Registers
Configuration Registers
USER MODEL UISA
2.3.1.2 MPC8260-Specic Registers
2-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 2-1 shows the bit denitions for HID0.
Table 2-1. HID0 Field Descriptions
MOTOROLA Chapter 2. PowerPC Processor Core 2-13
Table 2-1. HID0 Field Descriptions (Continued)
2-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 2-1. HID0 Field Descriptions (Continued)
MOTOROLA Chapter 2. PowerPC Processor Core 2-15
Figure 2-4. Hardware Implementation Register 1 (HID1)
Table 2-2 shows the bit denitions for HID1.
Table 2-3 describes the HID2 elds.
Figure 2-5. Hardware Implementation-Dependent Register 2 (HID2)
Table 2-2. HID1 Field Descriptions
Table 2-3. HID2 Field Descriptions
2.3.2 PowerPC Instruction Set and Addressing Modes
2.3.2.1 Calculating Effective Addresses
2.3.2.2 PowerPC Instruction Set
Page
2.3.2.3 MPC8260 Implementation-Specic Instruction Set
2.4 Cache Implementation
2.4.1 PowerPC Cache Model
2.4.2 MPC8260 Implementation-Specic Cache Implementation
2.4.2.1 Data Cache
Page
2.4.2.2 Instruction Cache
2.4.2.3 Cache Locking
2.5 Exception Model
2.5.1 PowerPC Exception Model
2.5.2 MPC8260 Implementation-Specic Exception Model
2-24 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 2-4. Exception Classifications for the Processor Core
Table 2-5. Exceptions and Conditions
MOTOROLA Chapter 2. PowerPC Processor Core 2-25
Table 2-5. Exceptions and Conditions (Continued)
2-26 MPC8260 PowerQUICC II Users Manual MOTOROLA
2.5.3 Exception Priorities
2.6 Memory Management
Table 2-5. Exceptions and Conditions (Continued)
2.6.1 PowerPC MMU Model
2.6.2 MPC8260 Implementation-Specic MMU Features
2.7 Instruction Timing
2-30 MPC8260 PowerQUICC II Users Manual MOTOROLA
The new latency is reected in Table 2-6.
2.8 Differences between the MPC8260s Core and the PowerPC 603e Microprocessor
Table 2-6. Integer Divide Latency
Table 2-7. Major Differences between MPC8260s Core and the MPC603e Users Manual
MOTOROLA Chapter 2. PowerPC Processor Core 2-31
Page
Chapter 3 Memory Map
3-2 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 3. Memory Map 3-3
3-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 3. Memory Map 3-5
3-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 3. Memory Map 3-7
3-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 3. Memory Map 3-9
3-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 3. Memory Map 3-11
3-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 3. Memory Map 3-13
3-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
Part II Conguration and Reset
Audience
Page
Table v. Acronyms and Abbreviated Terms (Continued)
Page
Chapter 4 System Interface Unit (SIU)
4.1 System Conguration and Protection
4.1.1 Bus Monitor
4.1.2 Timers Clock
4.1.3 Time Counter (TMCNT)
4.1.4 Periodic Interrupt Timer (PIT)
4.1.5 Software Watchdog Timer
4.2 Interrupt Controller
4-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.2.1 Interrupt Conguration
Figure 4-8. MPC8260 Interrupt Structure
4.2.2 Interrupt Source Priorities
4-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 4-2. Interrupt Source Priority Levels (Continued)
MOTOROLA Chapter 4. System Interface Unit (SIU) 4-11
4.2.2.1 SCC, FCC, and MCC Relative Priority
4.2.2.2 PIT, TMCNT, and IRQ Relative Priority
4.2.2.3 Highest Priority Interrupt
4.2.3 Masking Interrupt Sources
4-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 4-9. Interrupt Request Masking
4.2.4 Interrupt Vector Generation and Calculation
Table 4-3. Encoding the Interrupt Vector
MOTOROLA Chapter 4. System Interface Unit (SIU) 4-15
Table 4-3. Encoding the Interrupt Vector (Continued)
4.2.4.1 Port C External Interrupts
4.3 Programming Model
4.3.1 Interrupt Controller Registers
4.3.1.1 SIU Interrupt Conguration Register (SICR)
4-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
The SICR register bits are described in Table 4-4.
4.3.1.2 SIU Interrupt Priority Register (SIPRR)
Figure 4-11. SIU Interrupt Priority Register (SIPRR)
Table 4-4. SICR Field Descriptions
MOTOROLA Chapter 4. System Interface Unit (SIU) 4-19
The SIPRR register bits are described in Table 4-5.
4.3.1.3 CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L)
Figure 4-12. CPM High Interrupt Priority Register (SCPRR_H)
Table 4-5. SIPRR Field Descriptions
4-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 4-6 describes SCPRR_H elds.
Table 4-7 describes SCPRR_L elds.
Table 4-6. SCPRR_H Field Descriptions
Figure 4-13. CPM Low Interrupt Priority Register (SCPRR_L) Table 4-7. SCPRR_L Field Descriptions
MOTOROLA Chapter 4. System Interface Unit (SIU) 4-21
4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)
Figure 4-15 shows SIPNR_L elds.
Figure 4-14. SIPNR_H Fields
Figure 4-15. SIPNR_L Fields
Table 4-7. SCPRR_L Field Descriptions (Continued)
4.3.1.5 SIU Interrupt Mask Registers (SIMR_H and SIMR_L)
4.3.1.6 SIU Interrupt Vector Register (SIVEC)
4-24 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 4-19. Interrupt Table Handling Example
4.3.1.7 SIU External Interrupt Control Register (SIEXR)
4-25
Table 4-8 describes SIEXR elds.
The system conguration and protection registers are described in the following sections.
4.3.2.1 Bus Conguration Register (BCR)
4.3.2 System Conguration and Protection Registers
Figure 4-20. SIU External Interrupt Control Register (SIEXR) Table 4-8. SIEXR Field Descriptions
4-26
Table 4-9 describes BCR elds.
Figure 4-21. Bus Configuration Register (BCR) Table 4-9. BCR Field Descriptions
4-27
Table 4-9. BCR Field Descriptions (Continued)
4.3.2.3 60x Bus Arbitration-Level Registers (PPC_ALRH/PPC_ALRL)
4-28
Figure 4-22. PPC_ACR Table 4-10. PPC_ACR Field Descriptions
4-29
4.3.2.4 Local Bus Arbiter Conguration Register (LCL_ACR)
Figure 4-23. PPC_ALRH
4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and LCL_ACRL)
LCL_ALRL, shown in Figure 4-27, denes arbitration priority of MPC8260 local bus masters 815.
Table 4-11. LCL_ACR Field Descriptions
4.3.2.6 SIU Module Conguration Register (SIUMCR)
Figure 4-28. SIU Model Configuration Register (SIUMCR)
Figure 4-27. LCL_ALRL
4-32 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 4-12 describes SIUMCR elds.
Table 4-12. SIUMCR Register Field Descriptions
4-33 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 4-12. SIUMCR Register Field Descriptions (Continued)
4-34 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.2.7 Internal Memory Map Register (IMMR)
Table 4-13 describes IMMR elds.
Figure 4-29. Internal Memory Map Register (IMMR) Table 4-13. IMMR Field Descriptions
4-35 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.2.8 System Protection Control Register (SYPCR)
Table 4-14 describes SYPCR elds.
Figure 4-30. System Protection Control Register (SYPCCR) Table 4-14. SYPCR Field Descriptions
4-36 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.2.9 Software Service Register (SWSR)
Table 4-15 describes TESCR1 elds.
4.3.2.10 60x Bus Transfer Error Status and Control Register 1 (TESCR1)
The 60x bus transfer error status and control register 1 (TESCR1) is shown in Figure 4-31.
4-37 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.2.11 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
The 60x bus transfer error status and control register 2 (TESCR2) is shown in Figure 4-32.
Figure 4-32. 60x Bus Transfer Error Status and Control Register 2 (TESCR2)
Table 4-15. TESCR1 Field Descriptions (Continued)
4-38 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.2.12 Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
Figure 4-33. Local Bus Transfer Error Status and Control Register 1 (L_TESCR1)
The local bus transfer error status and control register 1 (L_TESCR1) is shown in Figure 4-33.
Table 4-16. TESCR2 Field Descriptions
4-39 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.2.13 Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)
Figure 4-34. Local Bus Transfer Error Status and Control Register 2 (L_TESCR2)
The local bus transfer error status and control register 2 (L_TESCR2) is shown in Figure 4-34.
Table 4-17. L_TESCR1 Field Descriptions
4-40 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.2.14 Time Counter Status and Control Register (TMCNTSC)
Table 4-19 describes TMCNTSC elds.
Table 4-18. L_TESCR2 Field Descriptions
4-41 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.2.15 Time Counter Register (TMCNT)
Figure 4-36. Time Counter Register (TCMCNT)
4.3.2.16 Time Counter Alarm Register (TMCNTAL)
Table 4-19. TMCNTSC Field Descriptions (Continued)
4-42 MPC8260 PowerQUICC II Users Manual MOTOROLA
4.3.3 Periodic Interrupt Registers
Figure 4-38. Periodic Interrupt Status and Control Register (PISCR)
The periodic interrupt registers are described in the following sections.
4.3.3.1 Periodic Interrupt Status and Control Register (PISCR)
Figure 4-37. Time Counter Alarm Register (TMCNTAL) Table 4-20. TMCNTAL Field Descriptions
4.3.3.2 Periodic Interrupt Timer Count Register (PITC)
Figure 4-39. Periodic interrupt Timer Count Register (PITC)
Table 4-21. PISCR Field Descriptions
4.3.3.3 Periodic Interrupt Timer Register (PITR)
4.4 SIU Pin Multiplexing
MOTOROLA Chapter 4. System Interface Unit (SIU) 4-45
Table 4-24.
Table 4-24. SIU Pins Multiplexing Control
Pin Name Pin Conguration Control
Page
Chapter 5 Reset
5.1 Reset Causes
5.1.1 Reset Actions
5.1.2 Power-On Reset Flow
5.1.3 HRESET Flow
5.1.4 SRESET Flow
5-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
5.2 Reset Status Register (RSR)
Table 5-3 describes RSR elds.
Figure 5-1. Reset Status Register (RSR) Table 5-3. RSR Field Descriptions
MOTOROLA Chapter 5. Reset 5-5
5.3 Reset Mode Register (RMR)
Table 5-4 describes RMR elds.
The reset mode register (RMR), shown in Figure 5-2, is memory-mapped into the SIU register map.
Figure 5-2. Reset Mode Register (RMR) Table 5-4. RMR Field Descriptions
Table 5-3. RSR Field Descriptions (Continued)
5.4 Reset Conguration
Page
5-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
5.4.1 Hard Reset Conguration Word
The contents of the hard reset conguration word are shown in Figure 5-3.
Table 5-7 describes hard reset conguration word elds.
MOTOROLA Chapter 5. Reset 5-9
5.4.2 Hard Reset Conguration Examples
This section presents some examples of hard reset congurations in different systems.
5.4.2.1 Single MPC8260 with Default Conguration
Table 5-7. Hard Reset Configuration Word Field Descriptions (Continued)
5.4.2.2 Single MPC8260 Congured from Boot EPROM
5.4.2.3 Multiple MPC8260s Congured from Boot EPROM
MOTOROLA Chapter 5. Reset 5-11
Figure 5-6. Configuring Multiple Chips
5.4.2.4 Multiple MPC8260s in a System with No EPROM
Part III The Hardware Interface
Page
Page
Part III-iv MPC8260 PowerQUICC II Users Manual MOTOROLA
Table vi. Acronyms and Abbreviated Terms (Continued)
Page
Page
Chapter 6 External Signals
6.1 Functional Pinout
Figure 6-1. MPC8260 External Signals
6.2 Signal Descriptions
M P
8 2 6 0
MOTOROLA Chapter 6. External Signals 6-3
Table 6-1. External Signals
6-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 6. External Signals 6-5
6-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 6. External Signals 6-7
6-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 6. External Signals 6-9
6-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 6. External Signals 6-11
6-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Note that CPM port multiplexing is described in the Chapter 35, Parallel I/O Ports.
Chapter 7 60x Signals
7-2 MPC8260 PowerQUICC II Users Manual MOTOROLA
7.1 Signal Conguration
Figure 7-1. PowerPC Signal Groupings
7.2 Signal Descriptions
7.2.1 Address Bus Arbitration Signals
7.2.1.1 Bus Request (BR)Output
7.2.1.2 Bus Grant (BG)
7.2.1.3 Address Bus Busy (ABB)
7.2.2 Address Transfer Start Signal
7.2.2.1 Transfer Start (TS)
7.2.2.2 Transfer Start (TS)Input
7.2.3 Address Transfer Signals
7.2.3.1 Address Bus (A[031])
7.2.4 Address Transfer Attribute Signals
7.2.4.1 Transfer Type (TT[04])
7.2.4.2 Transfer Size (TSIZ[03])
7.2.4.3 Transfer Burst (TBST)
7.2.4.4 Global (GBL)
7.2.4.5 Caching-Inhibited (CI)Output
7.2.4.6 Write-Through (WT)Output
7.2.5 Address Transfer Termination Signals
7.2.5.1 Address Acknowledge (AACK)
7.2.5.2 Address Retry (ARTRY)
7.2.6 Data Bus Arbitration Signals
7.2.6.1 Data Bus Grant (DBG)
7.2.6.2 Data Bus Busy (DBB)
7.2.7 Data Transfer Signals
7.2.7.1 Data Bus (D[063])
7.2.7.2 Data Bus Parity (DP[07])
7.2.8 Data Transfer Termination Signals
7.2.8.1 Transfer Acknowledge (TA)
7.2.8.2 Transfer Error Acknowledge (TEA)
7.2.8.3 Partial Data Valid Indication (PSDVAL)
Page
Chapter 8 The 60x Bus
8.1 Terminology
8.2 Bus Conguration
8.2.1 Single MPC8260 Bus Mode
8.2.2 60x-Compatible Bus Mode
8-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 8-2. 60x-Compatible Bus Mode
8.3 60x Bus Protocol Overview
8.3.1 Arbitration Phase
Page
8.3.2 Address Pipelining and Split-Bus Transactions
8.4 Address Tenure Operations
8.4.1 Address Arbitration
Page
8.4.2 Address Pipelining
8-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 8-5. Address Pipelining
8.4.3 Address Transfer Attribute Signals
8.4.3.1 Transfer Type Signal (TT[04]) Encoding
Table 8-2. Transfer Type Encoding
MOTOROLA Chapter 8. The 60x Bus 8-11
Table 8-2. Transfer Type Encoding (Continued)
8-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 8-2. Transfer Type Encoding (Continued)
8.4.3.2 Transfer Code Signals TC[02]
8.4.3.3 TBST and TSIZ[03] Signals and Size of Transfer
8.4.3.4 Burst Ordering During Data Transfers
8.4.3.5 Effect of Alignment on Data Transfers
Page
8.4.3.6 Effect of Port Size on Data Transfers
MOTOROLA Chapter 8. The 60x Bus 8-17
Figure 8-6. Interface to Different Port Size Devices
8-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 8-9 lists data transfer patterns for write cycles for accesses initiated by the MPC8260.
Table 8-8. Data Bus Requirements For Read Cycle
MOTOROLA Chapter 8. The 60x Bus 8-19
8.4.3.7 60x-Compatible Bus ModeSize Calculation
Table 8-9. Data Bus Contents for Write Cycles
8-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
8.4.3.8 Extended Transfer Mode
Table 8-10. Address and Size State Calculations
MOTOROLA Chapter 8. The 60x Bus 8-21
Table 8-11. Data Bus Contents for Extended Write Cycles
Table 8-12. Data Bus Requirements for Extended Read Cycles
8-22 MPC8260 PowerQUICC II Users Manual MOTOROLA
Extended transfer mode is enabled by setting the BCR[ETM].
Table 8-13. Address and Size State for Extended Transfers
8.4.4 Address Transfer Termination
8.4.4.1 Address Retried with ARTRY
Page
8.4.4.2 Address Tenure Timing Conguration
8.4.5 Pipeline Control
8.5 Data Tenure Operations
8.5.1 Data Bus Arbitration
8.5.2 Data Streaming Mode
8.5.3 Data Bus Transfers and Normal Termination
8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration
8.5.5 Port Size Data Bus Transfers and PSDVAL Termination
Page
8.5.6 Data Bus Termination by Assertion of TEA
8.6 Memory CoherencyMEI Protocol
8.7 Processor State Signals
8.7.1 Support for the lwarx/stwcx. Instruction Pair
8.7.2 TLBISYNC Input
8.8 Little-Endian Mode
Page
Chapter 9 Clocks and Power Control
9.1 Clock Unit
9-2 MPC8260 PowerQUICC II Users Manual MOTOROLA
9.2 Clock Conguration
Table 9-1. Clock Default Modes
Table 9-2. Clock Configuration Modes
MOTOROLA Chapter 9. Clocks and Power Control 9-3
Table 9-2. Clock Configuration Modes (Continued)
9-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 9-2. Clock Configuration Modes (Continued)
9.3 External Clock Inputs
9.4 Main PLL
9.4.1 PLL Block Diagram
9.4.2 Skew Elimination
9.5 Clock Dividers
9.6 The MPC8260s Internal Clock Signals
9.6.1 General System Clocks
9.7 PLL Pins
9-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 9-2. PLL Filtering Circuit
9.8 System Clock Control Register (SCCR)
Table 9-4 describes SCCR elds.
Figure 9-3. System Clock Control Register (SCCR) Table 9-4. SCCR Field Descriptions
MOTOROLA Chapter 9. Clocks and Power Control 9-9
9.9 System Clock Mode Register (SCMR)
Table 9-5 describes SCMR elds.
Figure 9-4. System Clock Mode Register (SCMR) Table 9-5. SCMR Field Descriptions
Table 9-4. SCCR Field Descriptions
9.10 Basic Power Structure
Chapter 10 Memory Controller
Page
MOTOROLA Chapter 10. Memory Controller 10-3
Figure 10-1. Dual-Bus Architecture
10.1 Features
Page
10.2 Basic Architecture
Page
Page
10.2.1 Address and Address Space Checking
10.2.2 Page Hit Checking
10.2.3 Error Checking and Correction (ECC)
10.2.4 Parity Generation and Checking
10.2.5 Transfer Error Acknowledge (TEA) Generation
10.2.6 Machine Check Interrupt (MCP) Generation
10.2.7 Data Buffer Controls (BCTLx)
10.2.8 Atomic Bus Operation
10.2.9 Data Pipelining
10.2.10 External Memory Controller Support
10.2.11 External Address Latch Enable Signal (ALE)
10.2.12 ECC/Parity Byte Select (PBSE)
10.2.13 Partial Data Valid Indication (PSDVAL)
MOTOROLA Chapter 10. Memory Controller 10-13
Figure 10-5. Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer
10.3 Register Descriptions
Table 10-2 lists registers used to control the 60x bus memory controller.
Table 10-2. 60x Bus Memory Controller Registers
Internal
10-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
10.3.1 Base Registers (BRx)
Table 10-3 describes BRx elds.
Figure 10-6. Base Registers (BRx) Table 10-3. BRx Field Descriptions
MOTOROLA Chapter 10. Memory Controller 10-15
Table 10-3. BRx Field Descriptions (Continued)
10.3.2 Option Registers (ORx)
MOTOROLA Chapter 10. Memory Controller 10-17
Table 10-4. ORx Field Descriptions (SDRAM Mode) (Continued)
10-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-8 shows ORx as it is formatted for GPCM mode.
Table 10-5 describes ORx elds in GPCM mode.
1 11 0 1111 0 1 0 0
Figure 10-8. ORx GPCM Mode Table 10-5. ORxGPCM Mode Field Descriptions
Table 10-4. ORx Field Descriptions (SDRAM Mode) (Continued)
Table 10-5. ORxGPCM Mode Field Descriptions (Continued)
10-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-9 shows ORx as it is formatted for UPM mode.
Table 10-6 describes the ORx elds in UPM mode.
Figure 10-9. ORxUPM Mode Table 10-6. Option Register (ORx)UPM Mode
MOTOROLA Chapter 10. Memory Controller 10-21
10.3.3 60x SDRAM Mode Register (PSDMR)
Table 10-7 describes PSMDR elds. LSMDR elds are described in Table 10-8.
CL
Figure 10-10. 60x/Local SDRAM Mode Register (PSDMR/LSDMR) Table 10-7. PSDMR Field Descriptions
10-22 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 10-7. PSDMR Field Descriptions (Continued)
MOTOROLA Chapter 10. Memory Controller 10-23
Table 10-7. PSDMR Field Descriptions (Continued)
10-24 MPC8260 PowerQUICC II Users Manual MOTOROLA
10.3.4 Local Bus SDRAM Mode Register (LSDMR)
Table 10-8. LSDMR Field Descriptions
MOTOROLA Chapter 10. Memory Controller 10-25
Table 10-8. LSDMR Field Descriptions (Continued)
10-26 MPC8260 PowerQUICC II Users Manual MOTOROLA
10.3.5 Machine A/B/C Mode Registers (MxMR)
100
Figure 10-11. Machine x Mode Registers (MxMR)
Table 10-8. LSDMR Field Descriptions (Continued)
MOTOROLA Chapter 10. Memory Controller 10-27
Table 10-9 describes MxMR bits.
Table 10-9. Machine x Mode Registers (MxMR)
10-28 MPC8260 PowerQUICC II Users Manual MOTOROLA
10.3.6 Memory Data Register (MDR)
Table 10-9. Machine x Mode Registers (MxMR) (Continued)
MOTOROLA Chapter 10. Memory Controller 10-29
Table 10-10 describes MDR elds.
10.3.7 Memory Address Register (MAR)
Figure 10-13. Memory Address Register (MAR)
The memory address register (MAR) is shown in Figure 10-13.
Figure 10-12. Memory Data Register (MDR) Table 10-10. MDR Field Descriptions
10-30 MPC8260 PowerQUICC II Users Manual MOTOROLA
10.3.8 60x Bus-Assigned UPM Refresh Timer (PURT)
The local bus assigned UPM refresh timer register (LURT) is shown in Figure 10-15.
The 60x bus assigned UPM refresh timer register (PURT) is shown in Figure 10-14.
Table 10-12 describes PURT elds.
10.3.9 Local Bus-Assigned UPM Refresh Timer (LURT)
10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
Table 10-14 describes PSRT elds.
The 60x bus assigned SDRAM refresh timer register (PSRT) is shown in Figure 10-16.
Table 10-13. Local Bus-Assigned UPM Refresh Timer (LURT)
10-32 MPC8260 PowerQUICC II Users Manual MOTOROLA
10.3.11 Local Bus-Assigned SDRAM Refresh Timer (LSRT)
The local bus-assigned SDRAM refresh timer register (LSRT) is shown in Figure 10-17.
Table 10-16 describes MPTPR elds.
Table 10-15 describes LSRT elds.
10.3.12 Memory Refresh Timer Prescaler Register (MPTPR)
10.4 SDRAM Machine
10-34 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-19. 128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown)
10.4.1 Supported SDRAM Congurations
10.4.2 SDRAM Power-On Initialization
10.4.3 JEDEC-Standard SDRAM Interface Commands
10.4.4 Page-Mode Support and Pipeline Accesses
10.4.5 Bank Interleaving
10.4.5.1 SDRAM Address Multiplexing (SDAM and BSMA)
10.4.6 SDRAM Device-Specic Parameters
10.4.6.1 Precharge-to-Activate Interval
MOTOROLA Chapter 10. Memory Controller 10-39
Figure 10-20. PRETOACT = 2 (2 Clock Cycles)
10.4.6.2 Activate to Read/Write Interval
This parameter, controlled by P/LSDMR[ACTTORW], denes the earliest timing for
READ/WRITE command after an ACTIVATE command.
Figure 10-21. ACTTORW = 2 (2 Clock Cycles)
10-40 MPC8260 PowerQUICC II Users Manual MOTOROLA
10.4.6.3 Column Address to First Data OutCAS Latency
Figure 10-22. CL = 2 (2 Clock Cycles)
10.4.6.4 Last Data Out to Precharge
This parameter, controlled by P/LSDMR[LDOTOPRE], denes the earliest timing for the
PRECHARGE command after the last data was read from the SDRAM. It is always related to
10.4.6.5 Last Data In to PrechargeWrite Recovery
Figure 10-24. WRC = 2 (2 Clock Cycles)
10.4.6.6 Refresh Recovery Interval (RFRC)
This parameter, controlled by P/LSDMR[RFRC], denes the earliest timing for an
ACTIVATE command after a REFRESH command.
10.4.6.8 External Address and Command Buffers (BUFCMD)
10.4.7 SDRAM Interface Timing
MOTOROLA Chapter 10. Memory Controller 10-43
Figure 10-28. SDRAM Single-Beat Read, Page Closed, CL = 3
Figure 10-29. SDRAM Single-Beat Read, Page Hit, CL = 3
Figure 10-30. SDRAM Two-Beat Burst Read, Page Closed, CL = 3
10-44 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3
Figure 10-32. SDRAM Single-Beat Write, Page Hit
Figure 10-33. SDRAM Three-Beat Burst Write, Page Closed
MOTOROLA Chapter 10. Memory Controller 10-45
Figure 10-34. SDRAM Read-after-Read Pipeline, Page Hit, CL = 3
Figure 10-35. SDRAM Write-after-Write Pipelined, Page Hit
Figure 10-36. SDRAM Read-after-Write Pipelined, Page Hit
10.4.8 SDRAM Read/Write Transactions
10.4.9 SDRAM MODE-SET Command Timing
10.4.10 SDRAM Refresh
10.4.11 SDRAM Refresh Timing
10.4.12 SDRAM Conguration Examples
10.4.12.1 SDRAM Conguration Example (Page-Based Interleaving)
Page
10.4.13 SDRAM Conguration Example (Bank-Based Interleaving)
10.5 General-Purpose Chip-Select Machine (GPCM)
10-52 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-40. GPCM-to-SRAM Conguration
10.5.1 Timing Conguration
Table 10-30. GPCM Strobe Signal Behavior
10.5.1.1 Chip-Select Assertion Timing
10.5.1.2 Chip-Select and Write Enable Deassertion Timing
MOTOROLA Chapter 10. Memory Controller 10-55
Figure 10-45. GPCM Memory Device Basic Timing (ACS 00, CSNT = 1, TRLX = 0)
10.5.1.3 Relaxed Timing
Figure 10-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)
Page
10.5.1.4 Output Enable (OE) Timing
10.5.1.5 Programmable Wait State Conguration
10.5.1.6 Extended Hold Time on Read Accesses
10-58 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-50 through Figure 10-53 show timing examples.
Figure 10-50. GPCM Read Followed by Read (ORx[2930] = 0x, Fastest Timing)
Table 10-31. TRLX and EHTR Combinations
MOTOROLA Chapter 10. Memory Controller 10-59
Figure 10-51. GPCM Read Followed by Read (ORx[2930] = 01)
Figure 10-52. GPCM Read Followed by Write (ORx[2930] = 01)
10.5.2 External Access Termination
10.5.3 Boot Chip-Select Operation
10.5.4 Differences between MPC8xxs GPCM and MPC8260s GPCM
10.6 User-Programmable Machines (UPMs)
Page
10.6.1 Requests
10.6.1.1 Memory Access Requests
10.6.1.2 UPM Refresh Timer Requests
10.6.1.3 Software RequestsRUN Command
10.6.1.4 Exception Requests
10.6.2 Programming the UPMs
10.6.3 Clock Timing
Page
10.6.4 The RAM Array
10-70 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-61. RAM Array and Signal Generation
10.6.4.1 RAM Words
Figure 10-62. The RAM Word
MOTOROLA Chapter 10. Memory Controller 10-71
Table 10-35 describes RAM word elds.
Table 10-35. RAM Word Bit Settings
10-72 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 10-35. RAM Word Bit Settings (Continued)
MOTOROLA Chapter 10. Memory Controller 10-73
Page
Page
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10.6.4.2 Address Multiplexing
10.6.4.3 Data Valid and Data Sample Control
10.6.4.4 Signals Negation
10.6.4.5 The Wait Mechanism
10.6.4.6 Extended Hold Time on Read Accesses
10.6.5 UPM DRAM Conguration Example
10.6.6 Differences between MPC8xx UPM and MPC8260 UPM
10.7 Memory System Interface Example Using UPM
10-82 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size)
Table 10-41. UPMs Attributes Example
MOTOROLA Chapter 10. Memory Controller 10-83
Figure 10-68. Single-Beat Read Access to FPM DRAM
10-84 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-69. Single-Beat Write Access to FPM DRAM
Figure 10-70. Burst Read Access to FPM DRAM (No LOOP)
MOTOROLA Chapter 10. Memory Controller 10-85
10-86 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-71. Burst Read Access to FPM DRAM (LOOP)
MOTOROLA Chapter 10. Memory Controller 10-87
Figure 10-72. Burst Write Access to FPM DRAM (No LOOP)
10-88 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-73. Refresh Cycle (CBR) to FPM DRAM
MOTOROLA Chapter 10. Memory Controller 10-89
Figure 10-74. Exception Cycle
Page
MOTOROLA Chapter 10. Memory Controller 10-91
Figure 10-75. FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN)
10-92 MPC8260 PowerQUICC II Users Manual MOTOROLA
10.7.0.1 EDO Interface Example
Figure 10-76. MPC8260/EDO Interface Connection to the 60x Bus
Table 10-43. EDO Connection Field Value Example
MOTOROLA Chapter 10. Memory Controller 10-93
Figure 10-77. Single-Beat Read Access to EDO DRAM
10-94 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-78. Single-Beat Write Access to EDO DRAM
MOTOROLA Chapter 10. Memory Controller 10-95
Figure 10-79. Single-Beat Write Access to EDO DRAM Using REDO to Insert Three Wait States
10-96 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-80. Burst Read Access to EDO DRAM
MOTOROLA Chapter 10. Memory Controller 10-97
Figure 10-81. Burst Write Access to EDO DRAM
10-98 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 10-82. Refresh Cycle (CBR) to EDO DRAM
MOTOROLA Chapter 10. Memory Controller 10-99
Figure 10-83. Exception Cycle For EDO DRAM
10.8 Handling Devices with Slow or Variable Access Times
10.8.1 Hierarchical Bus Interface Example
10.8.2 Slow Devices Example
10.9 External Master Support (60x-Compatible Mode)
10.9.1 60x-Compatible External Masters
10.9.2 MPC8260-Type External Masters
10.9.3 Extended Controls in 60x-Compatible Mode
10.9.4 Using BNKSEL SIgnals in Single-MPC8260 Bus Mode
10.9.5 Address Incrementing for External Bursting Masters
10.9.6 External Masters Timing
Page
10.9.6.1 Example of External Master Using the SDRAM Machine
MOTOROLA Chapter 10. Memory Controller 10-105
Figure 10-86. External Master Configuration with SDRAM Device
Page
Chapter 11 Secondary (L2) Cache Support
11.1 L2 Cache Congurations
11.1.1 Copy-Back Mode
11-2 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 11-1. L2 Cache in Copy-Back Mode
11.1.2 Write-Through Mode
Page
11-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 11-2. External L2 Cache in Write-Through Mode
11.1.3 ECC/Parity Mode
Page
11-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 11-3. External L2 Cache in ECC/Parity Mode
11.2 L2 Cache Interface Parameters
11.3 System Requirements When Using the L2 Cache Interface
11.4 L2 Cache Operation
11.5 Timing Example
MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-9
Figure 11-4. Read Access with L2 Cache
Page
Chapter 12 IEEE 1149.1 Test Access Port
12.1 Overview
12-2 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 12-1. Test Logic Block Diagram
The TAP consists of the signals in Table 12-1.
12.2 TAP Controller
Table 12-1. TAP Signals
12.3 Boundary Scan Register
12-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 12-3. Output Pin Cell (O.Pin)
Figure 12-4. Observe-Only Input Pin Cell (I.Obs)
12-5
12-6
Table 12-2. Boundary Scan Bit Definition
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
12-17
12-18
12-19
12-20
12-21
12-22
12-23
12-24
12-25
12-26
12-27
12-28
12.4 Instruction Register
12-29
Table 12-3. Instruction Decoding
12.5 MPC8260 Restrictions
12.6 Nonscan Chain Operation
Part IV
Communications Processor Module
Page
Page
Page
MOTOROLA Part IV. Communications Processor Module Part IV-v
Table vii. Acronyms and Abbreviated Terms
Part IV-vi MOTOROLA
Table vii. Acronyms and Abbreviated Terms (Continued)
MOTOROLA Part IV. Communications Processor Module Part IV-vii
Page
Chapter 13 Communications Processor Module
13.1 Features
Page
MOTOROLA Chapter 13. Communications Processor Module Overview 13-3
Figure 13-1. MPC8260 CPM Block Diagram
13.2 MPC8260 Serial Congurations
Table 13-1. Possible MPC8260 Applications
13.3 Communications Processor (CP)
13.3.1 Features
13.3.2 CP Block Diagram
MOTOROLA Chapter 13. Communications Processor Module Overview 13-5
Figure 13-2 shows the CP block diagram.
Figure 13-2. Communications Processor (CP) Block Diagram
13.3.3 PowerPC Core Interface
13.3.4 Peripheral Interface
13.3.5 Execution from RAM
13.3.6 RISC Controller Conguration Register (RCCR)
RCCR bit elds are described in Table 13-3.
13-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 13. Communications Processor Module Overview 13-9
13.3.7 RISC Time-Stamp Control Register (RTSCR)
Figure 13-4. RISC Time-Stamp Control Register (RTSCR)
Table 13-3. RISC Controller Configuration Register Field Descriptions (Continued)
13.3.8 RISC Time-Stamp Register (RTSR)
13.3.9 RISC Microcode Revision Number
13.4 Command Set
13.4.1 CP Command Register (CPCR)
13-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 13-6. CP Command Register Field Descriptions (Continued)
MOTOROLA Chapter 13. Communications Processor Module Overview 13-13
13.4.1.1 CP Commands
The CP command opcodes are shown in Table 13-7.
Table 13-7. CP Command Opcodes
13-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
The commands in Table 13-7 are described in Table 13-8.
Table 13-8. Command Descriptions
13.4.2 Command Register Example
13.4.3 Command Execution Latency
13.5 Dual-Port RAM
13-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 13-8. Dual-Port RAM Memory Map
13.5.1 Buffer Descriptors (BDs)
13.5.2 Parameter RAM
13-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
13.6 RISC Timer Tables
Table 13-10. Parameter RAM
13.6.1 RISC Timer Table Parameter RAM
13-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
13.6.2 RISC Timer Command Register (TM_CMD)
Figure 13-10. RISC Timer Command Register (TM_CMD)
Figure 13-10 shows the RISC timer command register (TM_CMD).
Table 13-11. RISC Timer Table Parameter RAM
13.6.3 RISC Timer Table Entries
13.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR)
13.6.5 SET TIMER Command
13.6.6 RISC Timer Initialization Sequence
13.6.7 RISC Timer Initialization Example
13.6.8 RISC Timer Interrupt Handling
13.6.9 RISC Timer Table Scan Algorithm
13.6.10 Using the RISC Timers to Track CP Loading
Page
14-2 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 14-1. SI Block Diagram
14.1 Features
14.2 Overview
MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-5
Figure 14-2. Various Configurations of a Single TDM Channel
Page
14.3 Enabling Connections to TSA
14.4 Serial Interface RAM
14.4.1 One Multiplexed Channel with Static Frames
14.4.2 One Multiplexed Channel with Dynamic Frames
14.4.3 Programming SI
RAM Entries
Chapter 14. Serial Interface with Time-Slot Assigner
14-11
RAM Entry (MCC = 0)
Page
Chapter 14. Serial Interface with Time-Slot Assigner
14.4.4 SI
RAM Programming Example
14.4.5 Static and Dynamic Routing
Page
14-16
Figure 14-9. Example: SI
x
RAM Dynamic Changes, TDMa and b, Same SI
RAM Size
14.5 Serial Interface Registers
MR)
14.5.2 SI Mode Registers (SI
14.5.1 SI Global Mode Registers (SI
Table 14-5 describes SIxMR elds.
14-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 14-11. SI Mode Registers (SIxMR) Table 14-5. SIxMR Field Descriptions
MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-19
Table 14-5. SIxMR Field Descriptions (Continued)
14-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 14-12 shows the one-clock delay from sync to data when xFSD = 01.
Figure 14-12. One-Clock Delay from Sync to Data (xFSD = 01)
Figure 14-13 shows the elimination of the single-clock delay shown in Figure 14-12 by clearing xFSD.
Figure 14-13. No Delay from Sync to Data (xFSD = 00)
Table 14-5. SIxMR Field Descriptions (Continued)
Figure 14-14 shows the effects of changing FE when CE = 1 with a 1-bit frame sync delay.
Figure 14-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01
Figure 14-15 shows the effects of changing FE when CE = 0 with a 1-bit frame sync delay.
Figure 14-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01
14-22 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 14-16 shows the effects of changing FE when CE = 1 with no frame sync delay.
Figure 14-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00
MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-23
Figure 14-17 shows the effects of changing FE when CE = 0 with no frame sync delay.
Figure 14-17. Falling Edge (FE) Effect When CE = 0 and xFSD = 00
14.5.3 SIx RAM Shadow Address Registers (SIxRSR)
14-24 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 14-6 describes SIxRSR elds.
14.5.4 SI Command Register (SIxCMDR)
Figure 14-19. SI Command Register (SIxCMDR)
Figure 14-18. SIx RAM Shadow Address Registers (SIxRSR) Table 14-6. SIxRSR Field Descriptions
MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-25
Table 14-7 describes SIxCMDR elds.
14.6 Serial Interface IDL Interface Support
Table 14-7. SIxCMDR Field Description
Figure 14-20. SI Status Registers (SIxSTR) Table 14-8. SIxSTR Field Descriptions
14.6.1 IDL Interface Example
MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-27
Figure 14-22. IDL Terminal Adaptor
Table 14-9. IDL Signal Descriptions
Page
14.6.2 IDL Interface Programming
Page
14.7 Serial Interface GCI Support
Page
14.7.1 SI GCI Activation/Deactivation Procedure
14.7.2 Serial Interface GCI Programming
14.7.2.1 Normal Mode GCI Programming
14.7.2.2 SCIT Programming
Page
Page
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Chapter 15 CPM Multiplexing
15-2 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 15-1. CPM Multiplexing Logic (CMX) Block Diagram
15.1 Features
15.2 Enabling Connections to TSA or NMSI
15.3 NMSI Conguration
MOTOROLA Chapter 15. CPM Multiplexing 15-5
Figure 15-3. Bank of Clocks
15-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
15.4 CMX Registers
The following sections describe the CMX registers.
Table 15-1. Clock Source Options
15.4.1 CMX UTOPIA Address Register (CMXUAR)
Page
MOTOROLA Chapter 15. CPM Multiplexing 15-9
Figure 15-6. Connection of the Slave Address
15-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 15-7. Multi-PHY Receive Address Multiplexing
15.4.2 CMX SI1 Clock Route Register (CMXSI1CR)
FCC1
FCC2
MOTOROLA Chapter 15. CPM Multiplexing 15-11
Addr
15.4.3 CMX SI2 Clock Route Register (CMXSI2CR)
Figure 15-8. CMX SI1 Clock Route Register (CMXSI1CR) Table 15-3. CMXSI1CR Field Descriptions
15-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 15-4 describes CMXSI2CR elds.
15.4.4 CMX FCC Clock Route Register (CMXFCR)
Figure 15-9. CMX SI2 Clock Route Register (CMXSI2CR) Table 15-4. CMXSI2CR Field Descriptions
Table 15-5 describes CMXFCR elds.
MOTOROLA Chapter 15. CPM Multiplexing 15-13
Figure 15-10. CMX FCC Clock Route Register (CMXFCR) Table 15-5. CMXFCR Field Descriptions
15-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
15.4.5 CMX SCC Clock Route Register (CMXSCR)
Table 15-5. CMXFCR Field Descriptions (Continued)
Table 15-6 describes CMXSCR elds.
MOTOROLA Chapter 15. CPM Multiplexing 15-15
Figure 15-11. CMX SCC Clock Route Register (CMXSCR) Table 15-6. CMXSCR Field Descriptions
15-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 15-6. CMXSCR Field Descriptions (Continued)
MOTOROLA Chapter 15. CPM Multiplexing 15-17
15.4.6 CMX SMC Clock Route Register (CMXSMR)
Table 15-6. CMXSCR Field Descriptions (Continued)
Table 15-7 describes CMXSMR elds.
15-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 15-12. CMX SMC Clock Route Register (CMXSMR) Table 15-7. CMXSMR Field Descriptions
Chapter 16 Baud-Rate Generators (BRGs)
16.1 BRG Conguration Registers 18 (BRGCx)
MOTOROLA Chapter 16. Baud-Rate Generators (BRGs) 16-3
Table 16-1 describes the BRGCx elds.
Table 16-2 shows the possible external clock sources for the BRGs.
Table 16-1. BRGCx Field Descriptions
16.2 Autobaud Operation on a UART
16.3 UART Baud Rate Examples
Page
MOTOROLA Chapter 17. Timers 17-1
Chapter 17 Timers
Figure 17-1. Timer Block Diagram
Pin assignments for TINx, TGATEx, and TOUTx are described in Section 35.5, Ports Tables.
17.1 Features
17.2 General-Purpose Timer Units
17.2.1 Cascaded Mode
17.2.2 Timer Global Conguration Registers (TGCR1 and TGCR2)
MOTOROLA Chapter 17. Timers 17-5
The TGCR2 register is shown in Figure 17-4.
Table 17-2 describes TGCR2 elds.
Figure 17-4. Timer Global Configuration Register 2 (TGCR2) Table 17-2. TGCR2 Field Descriptions
Table 17-1. TGCR1 Field Descriptions (Continued)
17-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
17.2.3 Timer Mode Registers (TMR1TMR4)
Table 17-3 describes TMR1TMR4 register elds.
Figure 17-5. Timer Mode Registers (TMR1TMR4) Table 17-3. TMRITMR4 Field Descriptions
Table 17-2. TGCR2 Field Descriptions (Continued)
MOTOROLA Chapter 17. Timers 17-7
17.2.4 Timer Reference Registers (TRR1TRR4)
Figure 17-6. Timer Reference Registers (TRR1TRR4)
Table 17-3. TMRITMR4 Field Descriptions (Continued)
17.2.5 Timer Capture Registers (TCR1TCR4)
17.2.6 Timer Counters (TCN1TCN4)
17.2.7 Timer Event Registers (TER1TER4)
Table 17-4 describes TER elds.
Table 17-4. TER Field Descriptions
Page
Chapter 18 SDMA Channels and IDMA Emulation
18.1 SDMA Bus Arbitration and Bus Transfers
18.2 SDMA Registers
18.2.1 SDMA Status Register (SDSR)
18.2.2 SDMA Mask Register (SDMR)
18.2.3 SDMA Transfer Error Address Registers (PDTEA and LDTEA)
18.2.4 SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM)
18.3 IDMA Emulation
18.4 IDMA Features
18.5 IDMA Transfers
18.5.1 Memory-to-Memory Transfers
Page
18.5.1.1 External Request Mode
18.5.1.2 Normal Mode
18.5.2 Memory to/from Peripheral Transfers
18.5.2.1 Dual-Address Transfers
18.5.2.2 Single Address (Fly-By) Transfers
18.5.3 Controlling 60x Bus Bandwidth
18.6 IDMA Priorities
18.7 IDMA Interface Signals
18.7.1 DREQx and DACKx
18.7.1.1 Level-Sensitive Mode
18.7.1.2 Edge-Sensitive Mode
18.7.2 DONEx
18.8 IDMA Operation
18.8.1 Auto Buffer and Buffer Chaining
18.8.2 IDMAx Parameter RAM
MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-17
Table 18-4. IDMAx Parameter RAM (Continued)
18-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
18.8.2.1 DMA Channel Mode (DCM)
Table 18-5 describes DCM bits.
Figure 18-8. DCM Parameters Table 18-5. DCM Field Descriptions
18-19 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 18-5. DCM Field Descriptions (Continued)
18-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
18.8.2.2 Data Transfer Types as Programmed in DCM
Table 18-6 summarizes the types of data transfers according to the DCM programming.
18.8.2.3 Programming DTS and STS
Table 18-6. IDMA Channel Data Transfer Operation
MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-21
Table 18-7 describes valid STS/DTS values for memory-to-memory operations.
Table 18-8 describes valid STS/DTS values for memory/peripheral operations.
Table 18-7. Valid Memory-to-Memory STS/DTS Values
Table 18-8. Valid STS/DTS Values for Peripherals
18.8.3 IDMA Performance
18.8.4 IDMA Event Register (IDSR) and Mask Register (IDMR)
18-23 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 18-9 describes IDSR/IDMR elds.
18.8.5 IDMA BDs
Figure 18-10. IDMA BD Structure
Figure 18-9. IDMA Event/Mask Registers (IDSR/IDMR) Table 18-9. IDSR/IDMR Field Descriptions
18-24 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 18-10 describes IDMA BD elds.
Table 18-10. IDMA BD Field Descriptions
18-25 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 18-10. IDMA BD Field Descriptions (Continued)
18.9 IDMA Commands
18.9.1 START_IDMA Command
18.9.2 STOP_IDMA Command
18.10 IDMA Bus Exceptions
18.10.1 Externally Recognizing IDMA Operand Transfers
18.11 Programming the Parallel I/O Registers
18.12 IDMA Programming Examples
18.12.1 Peripheral-to-Memory Mode (60x Bus to Local Bus)IDMA2
18-30 MPC8260 PowerQUICC II Users Manual MOTOROLA
18.12.2 Memory-to-Peripheral Fly-By Mode (Both on 60x Bus) IDMA3
Table 18-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)IDMA3
Table 18-15. Example: Peripheral-to-Memory ModeIDMA2 (Continued)
18-31 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 18-16. Example: Memory-to-Peripheral Fly-By Mode (on 60x)IDMA3 (Continued)
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Chapter 19 Serial Communications Controllers (SCCs)
19.1 Features
19.1.1 The General SCC Mode Registers (GSMR1GSMR4)
19-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 19-1 describes GSMR_H elds.
Table 19-1. GSMR_H Field Descriptions
MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-5
Table 19-1. GSMR_H Field Descriptions (Continued)
19-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 19-3 shows GSMR_L.
Table 19-2 describes GSMR_L elds.
Figure 19-3. GSMR_LGeneral SCC Mode Register (Low Order) Table 19-2. GSMR_L Field Descriptions
MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-7
Table 19-2. GSMR_L Field Descriptions (Continued)
19-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
19.1.2 Protocol-Specic Mode Register (PSMR)
19.1.3 Data Synchronization Register (DSR)
19.1.4 Transmit-on-Demand Register (TODR)
19.2 SCC Buffer Descriptors (BDs)
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19.3 SCC Parameter RAM
Table 19-4. SCC Parameter RAM Map for All Protocols (Continued)
19-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
19.3.1 SCC Base Addresses
19.3.2 Function Code Registers (RFCR and TFCR)
19-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 19-6 describes RFCRx/TFCRx elds.
19.3.3 Handling SCC Interrupts
Table 19-6. RFCRx /TFCRx Field Descriptions
Table 19-7. SCCx Event, Mask, and Status Registers
19.3.4 Initializing the SCCs
19.3.5 Controlling SCC Timing with RTS, CTS, and CD
19.3.5.1 Synchronous Protocols
MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-19
Figure 19-10. Output Delay from CTS Asserted for Synchronous Protocols
19-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 19-11. CTS Lost in Synchronous Protocols
19.3.5.2 Asynchronous Protocols
19-22 MPC8260 PowerQUICC II Users Manual MOTOROLA
19.3.6 Digital Phase-Locked Loop (DPLL) Operation
Figure 19-13. DPLL Receiver Block Diagram
Page
19.3.6.1 Encoding Data with a DPLL
MOTOROLA Chapter 19. Serial Communications Controllers (SCCs) 19-25
Figure 19-15. DPLL Encoding Examples
Table 19-9. DPLL Codings
19.3.7 Clock Glitch Detection
19.3.8 Reconguring the SCCs
19.3.8.1 General Reconguration Sequence for an SCC Transmitter
19.3.8.2 Reset Sequence for an SCC Transmitter
19.3.8.3 General Reconguration Sequence for an SCC Receiver
19.3.8.4 Reset Sequence for an SCC Receiver
19.3.8.5 Switching Protocols
19.3.9 Saving Power
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Chapter 20 SCC UART Mode
20.1 Features
20.2 Normal Asynchronous Mode
20.3 Synchronous Mode
20-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
20.4 SCC UART Parameter RAM
For UART mode, the protocol-specic area of the SCC parameter RAM is mapped as in Table 20-1.
Table 20-1. UART-Specific SCC Parameter RAM Memory Map
20.5 Data-Handling Methods: Character- or Message- Based
20-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
20.6 Error and Status Reporting
20.7 SCC UART Commands
The transmit commands in Table 20-2 are issued to the CP command register (CPCR).
Table 20-2. Transmit Commands
20.8 Multidrop Systems and Address Recognition
20.9 Receiving Control Characters
Table 20-4 describes the data structure used in control character recognition.
MOTOROLA Chapter 20. SCC UART Mode 20-9
20.10 Hunt Mode (Receiver)
20.11 Inserting Control Characters into the Transmit Data Stream
20.12 Sending a Break (Transmitter)
20.13 Sending a Preamble (Transmitter)
20.14 Fractional Stop Bits (Transmitter)
20-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 20-6 describes DSR elds.
20.15 Handling Errors in the SCC UART Controller
Table 20-6. DSR Fields Descriptions
Table 20-7. Transmission Errors
MOTOROLA Chapter 20. SCC UART Mode 20-13
Reception errors are described in Table 20-8.
20.16 UART Mode Register (PSMR)
Table 20-8. Reception Errors
Table 20-9 describes PSMR UART elds.
20-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 20. SCC UART Mode 20-15
20.17 SCC UART Receive Buffer Descriptor (RxBD)
Table 20-9. PSMR UART Field Descriptions (Continued)
20-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 20-7. SCC UART Receiving using RxBDs
MOTOROLA Chapter 20. SCC UART Mode 20-17
Figure 20-8 shows the SCC UART RxBD.
Table 20-10 describes RxBD status and control elds.
20-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
Section 19.2, SCC Buffer Descriptors (BDs), describes the data length and buffer pointer elds.
20.18 SCC UART Transmit Buffer Descriptor (TxBD)
Table 20-11 describes TxBD status and control elds.
Table 20-10. SCC UART RxBD Status and Control Field Descriptions (Continued)
20.19 SCC UART Event Register (SCCE) and Mask
20-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 20-10. SCC UART Interrupt Event Example
Figure 20-11. SCC UART Event Register (SCCE) and Mask Register (SCCM)
MOTOROLA Chapter 20. SCC UART Mode 20-21
Table 20-12 describes SCCE elds for UART mode.
20.20 SCC UART Status Register (SCCS)
Figure 20-12. SCC Status Register for UART Mode (SCCS)
The SCC UART status register (SCCS), shown in Figure 20-12, monitors the real-time status of RXD.
Table 20-12. SCCE/SCCM Field Descriptions for UART Mode
20.21 SCC UART Programming Example
20.22 S-Records Loader Application
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Chapter 21 SCC HDLC Mode
21.1 SCC HDLC Features
21.2 SCC HDLC Channel Frame Transmission
21.3 SCC HDLC Channel Frame Reception
21.4 SCC HDLC Parameter RAM
21-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 21-1. HDLC-Specific SCC Parameter RAM Memory Map
MOTOROLA Chapter 21. SCC HDLC Mode 21-5
Figure 21-2 shows 16- and 8-bit address recognition.
Figure 21-2. HDLC Address Recognition
21.5 Programming the SCC in HDLC Mode
21.6 SCC HDLC Commands
Table 21-2. Transmit Commands
21-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
Receive commands are described in Table 21-3.
21.7 Handling Errors in the SCC HDLC Controller
Reception errors are described in Table 21-5.
Table 21-3. Receive Commands
Table 21-4. Transmit Errors
Table 21-5. Receive Errors
21.8 HDLC Mode Register (PSMR)
Table 21-6 describes PSMR HDLC elds.
Figure 21-3. HDLC Mode Register (PSMR) Table 21-6. PSMR HDLC Field Descriptions
Table 21-5. Receive Errors (Continued)
10 0
21.9 SCC HDLC Receive Buffer Descriptor (RxBD)
The CP uses the RxBD, shown in Figure 21-4, to report on data received for each buffer.
Figure 21-4. SCC HDLC Receive Buffer Descriptor (RxBD)
Table 21-6. PSMR HDLC Field Descriptions (Continued)
MOTOROLA Chapter 21. SCC HDLC Mode 21-9
Table 21-7 describes HDLC RxBD status and control elds.
Descriptors (BDs). Because HDLC is a frame-based protocol, RxBD[Data Length] of the
Table 21-7. SCC HDLC RxBD Status and Control Field Descriptions
21-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 21-5. SCC HDLC Receiving Using RxBDs
MOTOROLA Chapter 21. SCC HDLC Mode 21-11
21.10 SCC HDLC Transmit Buffer Descriptor (TxBD)
The CP uses the TxBD, shown in Figure 21-6, to conrm transmissions and indicate error conditions.
Table 21-8 describes HDLC TxBD status and control elds.
21.11 HDLC Event Register (SCCE)/HDLC Mask
MOTOROLA Chapter 21. SCC HDLC Mode 21-13
Figure 21-8 shows interrupts that can be generated using the HDLC protocol.
Figure 21-8. SCC HDLC Interrupt Event Example
Table 21-9. SCCE/SCCM Field Descriptions (Continued)
21.12 SCC HDLC Status Register (SCCS)
21.13 SCC HDLC Programming Examples
21.13.1 SCC HDLC Programming Example #1
21.13.2 SCC HDLC Programming Example #2
21.14 HDLC Bus Mode with Collision Detection
Page
21.14.1 HDLC Bus Features
21.14.2 Accessing the HDLC Bus
21.14.3 Increasing Performance
21.14.4 Delayed RTS Mode
21.14.5 Using the Time-Slot Assigner (TSA)
21.14.6 HDLC Bus Protocol Programming
21.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol
21.14.6.2 HDLC Bus Controller Programming Example
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Chapter 22 SCC BISYNC Mode
22.1 Features
22.2 SCC BISYNC Channel Frame Transmission
22.3 SCC BISYNC Channel Frame Reception
22.4 SCC BISYNC Parameter RAM
Page
MOTOROLA Chapter 22. SCC BISYNC Mode 22-5
22.5 SCC BISYNC Commands
Receive commands are described in Table 22-2.
Table 22-2. Transmit Commands
Table 22-3. Receive Commands
22.6 SCC BISYNC Control Character Recognition
MOTOROLA Chapter 22. SCC BISYNC Mode 22-7
Table 22-4 describes control character table and RCCM elds.
22.7 BISYNC SYNC Register (BSYNC)
Figure 22-3. BISYNC SYNC (BSYNC)
Table 22-4. Control Character Table and RCCM Field Descriptions
22.8 SCC BISYNC DLE Register (BDLE)
22.9 Sending and Receiving the Synchronization Sequence
22.10 Handling Errors in the SCC BISYNC
22-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 22-8 describes transmit errors.
Table 22-9 describes receive errors.
22.11 BISYNC Mode Register (PSMR)
Table 22-8. Transmit Errors
Table 22-9. Receive Errors
MOTOROLA Chapter 22. SCC BISYNC Mode 22-11
Table 22-10 describes PSMR elds.
Table 22-10. PSMR Field Descriptions
22.12 SCC BISYNC Receive BD (RxBD)
MOTOROLA Chapter 22. SCC BISYNC Mode 22-13
Table 22-11. SCC BISYNC RxBD Status and Control Field Descriptions (Continued)
22-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
22.13 SCC BISYNC Transmit BD (TxBD)
Table 22-12 describes SCC BISYNC TxBD status and control elds.
22.14 BISYNC Event Register (SCCE)/BISYNC Mask
22-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 22-13 describes SCCE and SCCM elds.
22.15 SCC Status Registers (SCCS)
Figure 22-9. SCC Status Registers (SCCS)
Table 22-13. SCCE/SCCM Field Descriptions
22.16 Programming the SCC BISYNC Controller
22.17 SCC BISYNC Programming Example
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Chapter 23 SCC Transparent Mode
23.1 Features
23.2 SCC Transparent Channel Frame Transmission Process
23.3 SCC Transparent Channel Frame Reception Process
23.4 Achieving Synchronization in Transparent Mode
23.4.1 Synchronization in NMSI Mode
23.4.1.1 In-Line Synchronization Pattern
23.4.1.2 External Synchronization Signals
23.4.1.3 Transparent Mode without Explicit Synchronization
23.4.2 Synchronization and the TSA
23.4.2.1 Inline Synchronization Pattern
23.4.2.2 Inherent Synchronization
23.4.3 End of Frame Detection
23.5 CRC Calculation in Transparent Mode
23.6 SCC Transparent Parameter RAM
MOTOROLA Chapter 23. SCC Transparent Mode 23-7
23.7 SCC Transparent Commands
Table 23-2. SCC Transparent Parameter RAM Memory Map
Table 23-3. Transmit Commands
23-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 23-4 describes receive commands.
23.8 Handling Errors in the Transparent Controller
Table 23-6 describes receive errors.
Table 23-4. Receive Commands
Table 23-5. Transmit Errors
Table 23-6. Receive Errors
23.9 Transparent Mode and the PSMR
23.10 SCC Transparent Receive Buffer Descriptor (RxBD)
23.11 SCC Transparent Transmit Buffer Descriptor (TxBD)
Table 23-8 describes SCC Transparent TxBD status and control elds.
MOTOROLA Chapter 23. SCC Transparent Mode 23-11
23.12 SCC Transparent Event Register (SCCE)/Mask
23.13 SCC Status Register in Transparent Mode (SCCS)
23.14 SCC2 Transparent Programming Example
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Chapter 24 SCC Ethernet Mode
24.1 Ethernet on the MPC8260
24.2 Features
24.3 Connecting the MPC8260 to Ethernet
24.4 SCC Ethernet Channel Frame Transmission
24.5 SCC Ethernet Channel Frame Reception
24.6 The Content-Addressable Memory (CAM) Interface
24-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
24.7 SCC Ethernet Parameter RAM
For Ethernet mode, the protocol-specic area of the SCC parameter RAM is mapped as in Table 24-1.
Table 24-1. SCC Ethernet Parameter RAM Memory Map
MOTOROLA Chapter 24. SCC Ethernet Mode 24-9
Table 24-1. SCC Ethernet Parameter RAM Memory Map (Continued)
24-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
24.8 Programming the Ethernet Controller
24.9 SCC Ethernet Commands
Table 24-2. Transmit Commands
Table 24-1. SCC Ethernet Parameter RAM Memory Map (Continued)
24.10 SCC Ethernet Address Recognition
24-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 24-4. Ethernet Address Recognition Flowchart
24.11 Hash Table Algorithm
24.12 Interpacket Gap Time
24.13 Handling Collisions
24.14 Internal and External Loopback
24.15 Full-Duplex Ethernet Support
24.16 Handling Errors in the Ethernet Controller
MOTOROLA Chapter 24. SCC Ethernet Mode 24-15
Table 24-4 describes reception errors.
24.17 Ethernet Mode Register (PSMR)
Table 24-5. Reception Errors
Figure 24-5. Ethernet Mode Register (PSMR)
Table 24-4. Transmission Errors (Continued)
24-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 24-6 describes PSMR elds.
Table 24-6. PSMR Field Descriptions
MOTOROLA Chapter 24. SCC Ethernet Mode 24-17
24.18 SCC Ethernet Receive BD
The Ethernet controller uses the RxBD to report on the received data for each buffer.
Table 24-7 describes RxBD status and control elds.
Table 24-6. PSMR Field Descriptions
24-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 24-7. SCC Ethernet Receive RxBD Status and Control Field Descriptions (Continued)
MOTOROLA Chapter 24. SCC Ethernet Mode 24-19
Figure 24-7. Ethernet Receiving using RxBDs
24.19 SCC Ethernet Transmit Buffer Descriptor
24-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
conrm transmission or indicate errors so the core knows buffers have been serviced.
Table 24-8 describes TxBD status and control elds.
24.20 SCC Ethernet Event Register (SCCE)/Mask
24-22 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 24-10 shows an example of interrupts that can be generated in Ethernet protocol.
Figure 24-10. Ethernet Interrupt Events Example
Table 24-9. SCCE/SCCM Field Descriptions (Continued)
24.21 SCC Ethernet Programming Example
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Chapter 25 SCC AppleTalk Mode
25.1 Operating the LocalTalk Bus
25.2 Features
25.3 Connecting to AppleTalk
25.4 Programming the SCC in AppleTalk Mode
25.4.1 Programming the GSMR
25.4.2 Programming the PSMR
25.4.3 Programming the TODR
25.4.4 SCC AppleTalk Programming Example
Chapter 26 Serial Management Controllers (SMCs)
26.1 Features
26.2 Common SMC Settings and Congurations
26.2.1 SMC Mode Registers (SMCMR1/SMCMR2)
26-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 26-1 describes SMCMR elds.
Table 26-1. SMCMR1/SMCMR2 Field Descriptions
MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-5
26.2.2 SMC Buffer Descriptor Operation
Figure 26-3. SMC Memory Structure
Table 26-1. SMCMR1/SMCMR2 Field Descriptions (Continued)
26.2.3 SMC Parameter RAM
MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-7
To extract data from a partially full receive buffer, issue a CLOSE RXBD command.
Table 26-2. SMC UART and Transparent Parameter RAM Memory Map (Continued)
26.2.3.1 SMC Function Code Registers (RFCR/TFCR)
26.2.4 Disabling SMCs On-the-Fly
26.2.4.1 SMC Transmitter Full Sequence
26.2.4.2 SMC Transmitter Shortcut Sequence
26.2.4.3 SMC Receiver Full Sequence
26.2.4.4 SMC Receiver Shortcut Sequence
26.3 SMC in UART Mode
26.3.1 Features
26.3.2 SMC UART Channel Transmission Process
26.3.3 SMC UART Channel Reception Process
26.3.4 Programming the SMC UART Controller
26.3.5 SMC UART Transmit and Receive Commands
26.3.6 Sending a Break
26.3.7 Sending a Preamble
26.3.8 Handling Errors in the SMC UART Controller
26-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
26.3.9 SMC UART RxBD
Table 26-7 describes RxBD elds.
Figure 26-6. SMC UART RxBD Table 26-7. SMC UART RxBD Field Descriptions
Table 26-6. SMC UART Errors (Continued)
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26-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 26-7. RxBD Example
26.3.10 SMC UART TxBD
Page
26.3.11 SMC UART Event Register (SMCE)/Mask Register (SMCM)
26.3.12 SMC UART Controller Programming Example
26.4 SMC in Transparent Mode
26.4.1 Features
26.4.2 SMC Transparent Channel Transmission Process
26.4.3 SMC Transparent Channel Reception Process
26.4.4 Using SMSYN for Synchronization
MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-23
Figure 26-11. Synchronization with SMSYNx
26.4.5 Using the Time-Slot Assigner (TSA) for Synchronization
Page
MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-25
26.4.6 SMC Transparent Commands
The SMC uses BDs and the SMCE to report message send and receive errors.
Table 26-10 describes transmit commands issued to the CPCR.
Table 26-11 describes receive commands issued to the CPCR.
26.4.7 Handling Errors in the SMC Transparent Controller
26.4.8 SMC Transparent RxBD
Table 26-13 describes SMC transparent RxBD elds.
Figure 26-13. SMC Transparent RxBD Table 26-13. SMC Transparent RxBD Field Descriptions
MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-27
Descriptors (BDs).
26.4.9 SMC Transparent TxBD
Table 26-15 describes SMC transparent TxBD elds.
Table 26-14. SMC Transparent TxBD Table 26-15. SMC Transparent TxBD Field Descriptions
26.4.10 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
26.4.11 SMC Transparent NMSI Programming Example
26.5 The SMC in GCI Mode
26.5.1 SMC GCI Parameter RAM
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26-32 MPC8260 PowerQUICC II Users Manual MOTOROLA
26.5.4 SMC GCI Commands
The commands in Table 26-18 are issued to the CPCR.
Figure 26-16. SMC Monitor Channel TxBD
The CP uses this BD to report about the monitor channel transmit byte.
26.5.5 SMC GCI Monitor Channel RxBD
26.5.7 SMC GCI C/I Channel RxBD
Figure 26-18. SMC C/I Channel TxBD
The CP uses this BD to report about the C/I channel transmit byte.
26.5.8 SMC GCI C/I Channel TxBD
Table 26-20. SMC Monitor Channel TxBD Field Descriptions
26.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)
Chapter 27 Multi-Channel Controllers (MCCs)
27.1 Features
27.2 MCC Data Structure Organization
MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-3
Figure 27-1. BD Structure for One MCC
27.3 Global MCC Parameters
The global MCC parameters are described in Table 27-1.
Table 27-1. Global Multiple-Channel Parameters
27-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 27-1. Global Multiple-Channel Parameters (Continued)
27.4 Channel Extra Parameters
27.5 Super-Channel Table
27-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 27-3. Transmitter Super Channel Example
The example in Figure 27-5 shows a receiver super channel with slot synchronization.
MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-7
Figure 27-4. Receiver Super Channel with Slot Synchronization Example
The example in Figure 27-5 shows a receiver super channel without slot synchronization.
Figure 27-5. Receiver Super Channel without Slot Synchronization Example
27-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
27.6 Channel-Specic HDLC Parameters
Table 27-3 describes channel-specic parameters for HDLC.
Table 27-3. Channel-Specific Parameters for HDLC
27.6.1 Internal Transmitter State (TSTATE)
27.6.2 Interrupt Mask (INTMSK)
27.6.3 Channel Mode Register (CHAMR)
MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-11
27.6.4 Internal Receiver State (RSTATE)
Table 27-5. CHAMR Field Descriptions (Continued)
27-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
RSTATE high-byte elds are described in Table 27-6.
27.7 Channel-Specic Transparent Parameters
Table 27-7 describes channel-specic parameters for transparent operation.
Figure 27-9. Rx Internal State (RSTATE) High Byte Table 27-6. RSTATE High-Byte Field Descriptions
Table 27-7. Channel-Specific Parameters for Transparent Operation
MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-13
27.7.1 Channel Mode Register (CHAMR)Transparent Mode
Figure 27-10 shows the user-initialized channel mode register, CHAMR, for transparent mode.
Table 27-7. Channel-Specific Parameters for Transparent Operation (Continued)
CHAMR elds are described in Table 27-5,
27-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
27.8 MCC Conguration Registers (MCCFx)
27.9 MCC Commands
27.10 MCC Exceptions
27.10.1 MCC Event Register (MCCE)/Mask Register (MCCM)
MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-19
Table 27-13 describes MCCE elds.
27.10.1.1 Interrupt Table Entry
Table 27-13. MCCE/MCCM Register Field Descriptions
Table 27-14 describes interrupt circular table elds.
27-20 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 27. Multi-Channel Controllers (MCCs) 27-21
27.11 MCC Buffer Descriptors
RxBD elds are described in Table 27-15.
27.11.1 Receive Buffer Descriptor (RxBD)
Figure 27-15 shows the RxBD.
Figure 27-15. MCC Receive Buffer Descriptor (RxBD) Table 27-15. RxBD Field Descriptions
Table 27-15. RxBD Field Descriptions (Continued)
27.11.2 Transmit Buffer Descriptor (TxBD)
27.12 MCC Initialization and Start/Stop Sequence
27.12.1 Single-Channel Initialization
27.12.2 Super Channel Initialization
27.13 MCC Latency and Performance
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Chapter 28 Fast Communications Controllers (FCCs)
28.1 Overview
MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-3
Figure 28-1. FCC Block Diagram
28.2 General FCC Mode Registers (GFMRx)
Figure 28-2. General FCC Mode Register (GFMR)
28-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 28-1 describes GFMR elds.
Table 28-1. GFMR Register Field Descriptions
MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-5
Table 28-1. GFMR Register Field Descriptions (Continued)
28-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
28.3 FCC Protocol-Specic Mode Registers (FPSMRx)
28.4 FCC Data Synchronization Registers (FDSRx)
28.5 FCC Transmit-on-Demand Registers (FTODRx)
28.6 FCC Buffer Descriptors
Page
28.7 FCC Parameter RAM
Page
28-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 28-5. FCC Parameter RAM Common to All Protocols (Continued)
28.7.1 FCC Function Code Registers (FCRx)
28.8 Interrupts from the FCCs
28.8.1 FCC Event Registers (FCCEx)
28.8.2 FCC Mask Registers (FCCMx)
28.8.3 FCC Status Registers (FCCSx)
28.9 FCC Initialization
28.10 FCC Interrupt Handling
28.11 FCC Timing Control
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28-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 28-8. CTS Lost
28.12 Disabling the FCCs On-the-Fly
28.12.1 FCC Transmitter Full Sequence
28.12.2 FCC Transmitter Shortcut Sequence
28.12.3 FCC Receiver Full Sequence
28.12.4 FCC Receiver Shortcut Sequence
28.12.5 Switching Protocols
28.13 Saving Power
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Chapter 29 ATM Controller
29.1 Features
Page
29.2 ATM Controller Overview
29.2.1 Transmitter Overview
29.2.1.1 AAL5 Transmitter Overview
29.2.1.2 AAL1 Transmitter Overview
29.2.1.3 AAL0 Transmitter Overview
29.2.1.4 Transmit External Rate and Internal Rate Modes
29.2.2 Receiver Overview
29.2.2.1 AAL5 Receiver Overview
29.2.2.2 AAL1 Receiver Overview
29.2.2.3 AAL0 Receiver Overview
29.2.3 Performance Monitoring
29.2.4 ABR Flow Control
29.3 ATM Pace Control (APC) Unit
29.3.1 APC Modes and ATM Service Types
29.3.2 APC Unit Scheduling Mechanism
29.3.3 Determining the Scheduling Table Size
29.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table
29.3.3.2 Determining the Number of Slots in a Scheduling Table
29.3.4 Determining the Time-Slot Scheduling Rate of a Channel
29.3.5 ATM Trafc Type
29.3.5.1 Peak Cell Rate Trafc Type
29.3.5.2 Determining the PCR Trafc Type Parameters
29.3.5.3 Peak and Sustain Trafc Type (VBR)
29.3.5.4 Peak and Minimum Cell Rate Trafc Type (UBR+)
29.3.6 Determining the Priority of an ATM Channel
29.4 VCI/VPI Address Lookup Mechanism
29.4.1 External CAM Lookup
29.4.2 Address Compression
29-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-5. Address Compression Mechanism
Table 29-3. Field Descriptions for Address Compression
29.4.2.1 VP-Level Address Compression Table (VPLT)
29.4.2.2 VC-Level Address Compression Tables (VCLTs)
29.4.3 Misinserted Cells
29.4.4 Receive Raw Cell Queue
29.5 Available Bit Rate (ABR) Flow Control
29.5.1 The ABR Model
29.5.1.1 ABR Flow Control Source End-System Behavior
29.5.1.2 ABR Flow Control Destination End-System Behavior
29.5.1.3 ABR Flowcharts
29-23 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-12. ABR Transmit Flow (Continued)
29-24 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-13. ABR Transmit Flow (Continued)
29-25 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-14. ABR Receive Flow
29.5.2 RM Cell Structure
29-26 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.5.2.1 RM Cell Rate Representation
Figure 29-15. Rate Format for RM Cells
The rate (in cells/second) is calculated as in Figure 29-16.
Figure 29-16. Rate Formula for RM Cells
Table 29-7. Fields and their Positions in RM Cells
29.6 OAM Support
29.6.1 ATM-Layer OAM Denitions
29.6.2 Virtual Path (F4) Flow Mechanism
29.6.3 Virtual Channel (F5) Flow Mechanism
29.6.4 Receiving OAM F4 or F5 Cells
29.6.5 Transmitting OAM F4 or F5 Cells
29.6.6 Performance Monitoring
29.6.6.1 Running a Performance Block Test
29.6.6.2 PM Block Monitoring
29.6.6.3 PM Block Generation
29.6.6.4 BRC Performance Calculations
29.7 User-Dened Cells (UDC)
29.7.1 UDC Extended Address Mode (UEAD)
29.8 ATM Layer Statistics
29.9 ATM-to-TDM Interworking
29.9.1 Automatic Data Forwarding
29.9.2 Using Interrupts in Automatic Data Forwarding
29.9.3 Timing Issues
29.9.4 Clock Synchronization (SRTS and Adaptive FIFOs)
29.9.5 Mapping TDM Time Slots to VCs
29.9.6 CAS Support
29.9.7 Trunk Condition
29.10 ATM Memory Structure
29.10.1 Parameter RAM
29-38 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-11. ATM Parameter RAM Map
29-39 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-11. ATM Parameter RAM Map (Continued)
29-40 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.1.1 Determining UEAD_OFFSET (UEAD Mode Only)
29.10.1.2 VCI Filtering (VCIF)
Table 29-12. UEAD_OFFSETs for Extended Addresses in the UDC Extra Header
Figure 29-22. VCI Filtering Enable Bits Table 29-13. VCI Filtering Enable Field Descriptions
Table 29-11. ATM Parameter RAM Map (Continued)
29.10.1.3 Global Mode Entry (GMODE)
Figure 29-23 shows the layout of the global mode entry (GMODE). Table 29-14 describes GMODE elds.
29.10.2 Connection Tables (RCT, TCT, and TCTE)
Figure 29-23. Global Mode Entry (GMODE) Table 29-14. GMODE Field Descriptions
29.10.2.1 ATM Channel Code
29.10.2.2 Receive Connection Table (RCT)
Figure 29-25. Receive Connection Table (RCT) Entry
29-44 MPC8260 PowerQUICC II Users Manual MOTOROLA
29-45 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-16 describes RCT elds.
Table 29-16. RCT Field Descriptions
29-46 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-26. AAL5 Protocol-Specific RCT
Table 29-16. RCT Field Descriptions (Continued)
29-47 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-17 describes AAL5 protocol specic RCT elds.
Figure 29-27. AAL5-ABR Protocol-Specific RCT
Table 29-17. RCT Settings (AAL5 Protocol-Specific)
29-48 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-18 describes AAL5-ABR protocol-specic RCT elds.
Figure 29-28. AAL1 Protocol-Specific RCT
Table 29-19 describes AAL1 protocol-specic RCT elds.
Table 29-18. ABR Protocol-Specific RCT Field Descriptions
29-49 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-19. AAL1 Protocol-Specific RCT Field Descriptions
29-50 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-20 describes AAL0 protocol specic RCT elds.
Figure 29-29. AAL0 Protocol-Specific RCT Table 29-20. AAL0-Specific RCT Field Descriptions
Table 29-19. AAL1 Protocol-Specific RCT Field Descriptions (Continued)
29-51 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.2.3 Transmit Connection Table (TCT)
Figure 29-30 shows the format of an TCT entry.
Figure 29-30. Transmit Connection Table (TCT) Entry
Table 29-21 describes general TCT elds.
Table 29-20. AAL0-Specific RCT Field Descriptions (Continued)
Table 29-21. TCT Field Descriptions
29-53 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-21. TCT Field Descriptions (Continued)
29-54 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.2.3.1 AAL5 Protocol-Specic TCT Figure 29-31 shows the AAL5 protocol-specic TCT.
Table 29-22 describes AAL5 protocol-specic TCT elds.
29.10.2.3.2 AAL1 Protocol-Specic TCT Figure 29-32 shows the AAL1 protocol-specic TCT.
Figure 29-31. AAL5 Protocol-Specific TCT Table 29-22. AAL5-Specific TCT Field Descriptions
Figure 29-32. AAL1 Protocol-Specific TCT
Table 29-23 describes AAL1 protocol-specic TCT elds.
29.10.2.3.3 AAL0 Protocol-Specic TCT Figure 29-33 shows the AAL0 protocol-specic TCT.
Figure 29-33. AAL0 Protocol-Specific TCT
Table 29-23. AAL1-Specific TCT Field Descriptions
29-56 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-24 describes AAL0 protocol-specic TCT elds.
29.10.2.3.4 VBR Protocol-Specic TCTE Figure 29-34 shows the VBR protocol-specic TCTE.
Table 29-25 describes VBR protocol-specic TCTE elds.
Table 29-24. AAL0-Specific TCT Field Descriptions
29-57 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.2.3.5 UBR+ Protocol-Specic TCTE Figure 29-35 shows the UBR+ protocol-specic TCTE.
Table 29-26 describes UBR+ protocol-specic TCTE elds.
Table 29-25. VBR-Specific TCTE Field Descriptions (Continued)
29-58 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.2.3.6 ABR Protocol-Specic TCTE Figure 29-36 shows the ABR protocol-specic TCTE.
Table 29-27 describes ABR-specic TCTE elds.
Figure 29-36. ABR Protocol-Specific TCTE Table 29-27. ABR-Specific TCTE Field Descriptions
29-59 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-27. ABR-Specific TCTE Field Descriptions (Continued)
29.10.3 OAM Performance Monitoring Tables
29-61 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.4 APC Data Structure
Table 29-28. OAMPerformance Monitoring Table Field Descriptions
29-62 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-38. ATM Pace Control Data Structure
29.10.4.1 APC Parameter Tables
Table 29-29. APC Parameter Table
29.10.4.2 APC Priority Table
29.10.4.3 APC Scheduling Tables
29.10.5 ATM Controller Buffer Descriptors (BDs)
29.10.5.1 Transmit Buffer Operations
29.10.5.2 Receive Buffers Operation
Page
29-67 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-43. Receive Global Buffer Allocation Example
Figure 29-44. Free Buffer Pool Structure
Figure 29-45 describes the structure of a free buffer pool entry.
29-68 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-32 describes free buffer pool entry elds.
Figure 29-45. Free Buffer Pool Entry Table 29-32. Free Buffer Pool Entry Field Descriptions
Table 29-33. Free Buffer Pool Parameter Table
29-69 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.5.3 ATM Controller Buffers
Table 29-34 describes properties of the ATM receive and transmit buffers.
Figure 29-46 shows the AAL5 RxBD.
29.10.5.4 AAL5 RxBD
Table 29-34. Receive and Transmit Buffers
Table 29-35 describes AAL5 RxBD elds.
Table 29-35. AAL5 RxBD Field Descriptions
29-71 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.5.5 AAL1 RxBD
Figure 29-47 shows the AAL1 RxBD.
Figure 29-47. AAL1 RxBD
Table 29-35. AAL5 RxBD Field Descriptions (Continued)
29-72 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.5.6 AAL0 RxBD
Figure 29-48. AAL0 RxBD
Figure 29-48 shows the AAL0 RxBD.
Table 29-36. AAL1 RxBD Field Descriptions
29-73 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.5.7 AAL5, AAL1 User-Dened CellRxBD Extension
Table 29-37. AAL0 RxBD Field Descriptions
29.10.5.8 AAL5 TxBDs
Figure 29-50 shows the AAL5 TxBD.
29-75 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-38 describes AAL5 TxBD elds.
Table 29-38. AAL5 TxBD Field Descriptions
29-76 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.5.9 AAL1 TxBDs
Figure 29-51 shows the AAL1 TxBD.
Table 29-39 describes AAL1 TxBD elds.
Figure 29-51. AAL1 TxBD Table 29-39. AAL1 TxBD Field Descriptions
29-77 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.10.5.10 AAL0 TxBDs
Table 29-40 describes AAL0 TxBD elds.
Figure 29-52. AAL0 TxBDs Table 29-40. AAL0 TxBD Field Descriptions
29.10.5.11 AAL5, AAL1 User-Dened CellTxBD Extension
29.10.6 AAL1 Sequence Number (SN) Protection Table (AAL1 Only)
29.10.7 UNI Statistics Table
29.11 ATM Exceptions
29.11.1 Interrupt Queues
29-80 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-55. Interrupt Queue Structure
29.11.2 Interrupt Queue Entry
Figure 29-56. Interrupt Queue Entry
29-81 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-42 describes interrupt queue entry elds.
29.11.3 Interrupt Queue Parameter Tables
Table 29-42. Interrupt Queue Entry Field Description
Table 29-43. Interrupt Queue Parameter Table
29-82 MPC8260 PowerQUICC II Users Manual MOTOROLA
29.12 The UTOPIA Interface
Table 29-44 describes UTOPIA master mode signals.
29.12.1 UTOPIA Interface Master Mode
UTOPIA master signals are shown in Figure 29-57.
Figure 29-57. UTOPIA Master Mode Signals
29.12.1.1 UTOPIA Master Multiple PHY Operation
29.12.2 UTOPIA Interface Slave Mode
29-84 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 29-45 describes UTOPIA slave mode signals.
29.12.2.1 UTOPIA Slave Multiple PHY Operation
29.12.2.2 UTOPIA Clocking Modes
Table 29-45. UTOPIA Slave Mode Signals
29.12.2.3 UTOPIA Loop-Back Modes
29.13 ATM Registers
29.13.1 General FCC Mode Register (GFMR)
29.13.2 FCC Protocol-Specic Mode Register (FPSMR)
Table 29-47 describes FPSMR elds.
29-86 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 29-59. FCC ATM Mode Register (FPSMR) Table 29-47. FCC ATM Mode Register (FPSMR)
29.13.3 ATM Event Register (FCCE)/Mask Register (FCCM)
29.13.4 FCC Transmit Internal Rate Registers (FTIRRx)
Page
29.14 ATM Transmit Command
29.15 SRTS Generation and Clock Recovery Using External Logic
29.16 Conguring the ATM Controller for Maximum CPM Performance
29.16.1 Using Transmit Internal Rate Mode
29.16.2 APC Conguration
29.16.3 Buffer Conguration
Page
Chapter 30 Fast Ethernet Controller
30.1 Fast Ethernet on the MPC8260
30.2 Features
30.3 Connecting the MPC8260 to Fast Ethernet
30.4 Ethernet Channel Frame Transmission
Page
30.5 Ethernet Channel Frame Reception
30.6 Flow Control
30.7 CAM Interface
MOTOROLA Chapter 30. Fast Ethernet Controller 30-9
30.8 Ethernet Parameter RAM
For Ethernet mode, the protocol-specic area of the FCC parameter RAM is mapped as in Table 30-2.
Table 30-2. Ethernet-Specific Parameter RAM
30-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 30-2. Ethernet-Specific Parameter RAM (Continued)
MOTOROLA Chapter 30. Fast Ethernet Controller 30-11
30.9 Programming Model
30.10 Ethernet Command Set
MOTOROLA Chapter 30. Fast Ethernet Controller 30-13
Receive commands that apply to Ethernet are described in Table 30-4.
Table 30-4. Receive Commands
Table 30-3. Transmit Commands (Continued)
30-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
30.11 RMON Support
Table 30-5. RMON Statistics and Counters
MOTOROLA Chapter 30. Fast Ethernet Controller 30-15
30.12 Ethernet Address Recognition
Table 30-5. RMON Statistics and Counters (Continued)
30-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 30-4. Ethernet Address Recognition Flowchart
30.13 Hash Table Algorithm
30.14 Interpacket Gap Time
30.15 Handling Collisions
30.16 Internal and External Loopback
MOTOROLA Chapter 30. Fast Ethernet Controller 30-19
30.17 Ethernet Error-Handling Procedure
Reception errors are described in Table 30-7.
30.18 Fast Ethernet Registers
Table 30-6. Transmission Errors
Table 30-7. Reception Errors
30.18.1 FCC Ethernet Mode Register (FPSMR)
Table 30-8 describes FPSMR elds.
Figure 30-5. FCC Ethernet Mode Registers (FPSMR) Table 30-8. FPSMR Ethernet Field Descriptions
30.18.2 Ethernet Event Register (FCCE)/Mask Register (FCCM)
30-22 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 30-9 describes FCCE/FCCM elds.
Figure 30-7 shows interrupts that can be generated in the Ethernet protocol.
MOTOROLA Chapter 30. Fast Ethernet Controller 30-23
Figure 30-7. Ethernet Interrupt Events Example
30.19 Ethernet RxBDs
Table 30-10 describes Ethernet RxBD elds.
30-24 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 30-8. Fast Ethernet Receive Buffer (RxBD) Table 30-10. RxBD Field Descriptions
Page
30-26 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 30-9. Ethernet Receiving Using RxBDs
30.20 Ethernet TxBDs
Table 30-11 describes Ethernet TxBD elds.
MOTOROLA Chapter 30. Fast Ethernet Controller 30-27
Figure 30-10. Fast Ethernet Transmit Buffer (TxBD) Table 30-11. Ethernet TxBD Field Definitions
Page
Chapter 31 FCC HDLC Controller
31.1 Key Features
31.2 HDLC Channel Frame Transmission Processing
31.3 HDLC Channel Frame Reception Processing
31-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
31.4 HDLC Parameter RAM
Table 31-1. FCC HDLC-Specific Parameter RAM Memory Map
MOTOROLA Chapter 31. FCC HDLC Controller 31-5
Figure 31-2 shows an example of using HMASK and HADDR[14].
Figure 31-2. HDLC Address Recognition Example
31.5 Programming Model
31.5.1 HDLC Command Set
Table 31-2. Transmit Commands
31-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 31-3 describes the receive commands that apply to the HDLC controller.
31.5.2 HDLC Error Handling
Table 31-3. Receive Commands
Table 31-4. HDLC Transmission Errors
Table 31-2. Transmit Commands (Continued)
MOTOROLA Chapter 31. FCC HDLC Controller 31-7
31.6 HDLC Mode Register (FPSMR)
Table 31-5. HDLC Reception Errors
The FPSMR elds are described in Table 31-6.
31-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 31-3. HDLC Mode Register (FPSMR) Table 31-6. FPSMR Field Descriptions
31.7 HDLC Receive Buffer Descriptor (RxBD)
. . .
31-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 31-4. FCC HDLC Receiving Using RxBDs
MOTOROLA Chapter 31. FCC HDLC Controller 31-11
Figure 31-5 shows the FCC HDLC RxBD.
Table 31-7 describes RxBD elds.
Figure 31-5. FCC HDLC Receive Buffer Descriptor (RxBD) Table 31-7. RxBD field Descriptions
31.8 HDLC Transmit Buffer Descriptor (TxBD)
MOTOROLA Chapter 31. FCC HDLC Controller 31-13
Table 31-8 describes HDLC TxBD elds.
The TxBD status bits are written by the HDLC controller after sending the associated data buffer.
Table 31-8. HDLC TxBD Field Descriptions
31.9 HDLC Event Register (FCCE)/Mask Register (FCCM)
MOTOROLA Chapter 31. FCC HDLC Controller 31-15
Figure 31-8 shows interrupts that can be generated in the HDLC protocol.
Table 31-9. FCCE/FCCM Field Descriptions
31-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 31-8. HDLC Interrupt Event Example
31.10 FCC Status Register (FCCS)
Figure 31-9. FCC Status Register (FCCS)
MOTOROLA Chapter 31. FCC HDLC Controller 31-17
Table 31-10 describes FCCS bits.
Table 31-10. FCCS Register Field Descriptions
Page
Chapter 32 FCC Transparent Controller
32.1 Features
32.2 Transparent Channel Operation
32.3 Achieving Synchronization in Transparent Mode
32.3.1 In-Line Synchronization Pattern
32.3.2 External Synchronization Signals
32-4 MPC8260 PowerQUICC II Users Manual MOTOROLA
32.3.3 Transparent Synchronization Example
Figure 32-2 shows an example of synchronization using external signals.
Figure 32-2. Sending Transparent Frames between MPC8260s
Chapter 33 Serial Peripheral Interface (SPI)
33.1 Features
33.2 SPI Clocking and Signal Functions
33.3 Conguring the SPI Controller
33.3.1 The SPI as a Master Device
33.3.2 The SPI as a Slave Device
33.3.3 The SPI in Multimaster Operation
MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-5
Figure 33-3. Multimaster Configuration
33.4 Programming the SPI Registers
33.4.1 SPI Mode Register (SPMODE)
MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-7
Figure 33-5. SPI Transfer Format with SPMODE[CP] = 0
Figure 33-6. SPI Transfer Format with SPMODE[CP] = 1
Table 33-1. SPMODE Field Descriptions (Continued)
33.4.1.1 SPI Examples with Different SPMODE[LEN] Values
33.4.2 SPI Event/Mask Registers (SPIE/SPIM)
33.4.3 SPI Command Register (SPCOM)
33.5 SPI Parameter RAM
MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-11
Table 33-5. SPI Parameter RAM Memory Map (Continued)
33-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
33.5.1 Receive/Transmit Function Code Registers (RFCR/TFCR)
Figure 33-9 shows the elds in the receive/transmit function code registers (RFCR/TFCR)
Table 33-7 lists transmit/receive commands sent to the CP command register (CPCR).
33.6 SPI Commands
Figure 33-9. RFCR/TFCRFunction Code Registers Table 33-6. RFCR/TFCR Field Descriptions
Table 33-7. SPI Commands
33.7 The SPI Buffer Descriptor (BD) Table
33.7.1 SPI Buffer Descriptors (BDs)
33.7.1.1 SPI Receive BD (RxBD)
MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-15
33.7.1.2 SPI Transmit BD (TxBD)
Table 33-9 describes the TxBD status and control elds.
Figure 33-12. SPI TxBD Table 33-9. SPI TxBD Status and Control Field Descriptions
Table 33-8. SPI RxBD Status and Control Field Descriptions (Continued)
33.8 SPI Master Programming Example
33.9 SPI Slave Programming Example
33.10 Handling Interrupts in the SPI
Chapter 34 I2C Controller
34.1 Features
34.2 I2C Controller Clocking and Signal Functions
34.3 I2C Controller Transfers
34.3.1 I2C Master Write (Slave Read)
34.3.2 I2C Loopback Testing
34.3.3 I2C Master Read (Slave Write)
34.3.4 I2C Multi-Master Considerations
34.4 I2C Registers
34.4.1 I2C Mode Register (I2MOD)
MOTOROLA Chapter 34. I2C Controller 34-7
34.4.2 I2C Address Register (I2ADD)
The I2C address register, shown in Figure 34-7, holds the address for this I2C port.
Table 34-2 describes I2CADD elds.
34.4.3 I2C Baud Rate Generator Register (I2BRG)
The I2C baud rate generator register, shown in Figure 34-8, sets the divide ratio of the I2C BRG.
34.4.4 I2C Event/Mask Registers (I2CER/I2CMR)
34.4.5 I2C Command Register (I2COM)
MOTOROLA Chapter 34. I2C Controller 34-9
Table 34-5 describes I2COM elds.
34.5 I2C Parameter RAM
Figure 34-10. I2C Command Register (I2COM) Table 34-5. I2COM Field Descriptions
Table 34-6. I2C Parameter RAM Memory Map
34-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 34-6. I2C Parameter RAM Memory Map (Continued)
MOTOROLA Chapter 34. I2C Controller 34-11
Figure 34-11 shows the RFCR/TFCR bit elds.
Table 34-7 describes the RFCR/TFCR bit elds.
34.6 I2C Commands
Figure 34-11. I2C Function Code Registers (RFCR/TFCR) Table 34-7. RFCR/TFCR Field Descriptions
Table 34-8. I2C Transmit/Receive Commands
34.7 The I2C Buffer Descriptor (BD) Table
34.7.1 I2C Buffer Descriptors (BDs)
MOTOROLA Chapter 34. I2C Controller 34-13
34.7.1.1 I2C Receive Buffer Descriptor (RxBD)
Table 34-9 describes I2C RxBD status and control bits.
Figure 34-13. I2C RxBD Table 34-9. I2C RxBD Status and Control Bits
34-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
34.7.1.2 I2C Transmit Buffer Descriptor (TxBD)
Table 34-10 describes I2C TxBD status and control bits.
Figure 34-14. I2C TxBD Table 34-10. I2C TxBD Status and Control Bits
Chapter 35 Parallel I/O Ports
35.1 Features
35.2 Port Registers
35.2.1 Port Open-Drain Registers (PODRAPODRD)
35.2.2 Port Data Registers (PDATAPDATD)
MOTOROLA Chapter 35. Parallel I/O Ports 35-3
35.2.3 Port Data Direction Registers (PDIRAPDIRD)
Table 35-2 describes PDIR elds.
The port data direction register(PDIR), shown in Figure 35-3, is cleared at system reset.
Figure 35-2. Port Data Registers (PDATAPDATD)
Figure 35-3. Port Data Direction Register (PDIR) Table 35-2. PDIR Field Descriptions
35.2.4 Port Pin Assignment Register (PPAR)
The port pin assignment register (PPAR) is cleared at system reset.
Table 35-2 describes PPARx elds.
35.2.5 Port Special Options Registers AD (PSORAPSORD)
Figure 35-5 shows the port special options registers (PSORx).
NOTE
Figure 35-5. Special Options Registers (PSORAPOSRD) Table 35-4. PSORx Field Descriptions
35-6 MPC8260 PowerQUICC II Users Manual MOTOROLA
35.3 Port Block Diagram
Figure 35-6 shows the functional block diagram.
Figure 35-6. Port Functional Operation
35.4 Port Pins Functions
Each pin can operate as a general purpose I/O pin or as a dedicated input or output pin.
35.5 Ports Tables
35-8 MPC8260 PowerQUICC II Users Manual MOTOROLA
Figure 35-7. Primary and Secondary Option Programming
Table 35-5. Port ADedicated Pin Assignment (PPARA = 1)
MOTOROLA Chapter 35. Parallel I/O Ports 35-9
35-10 MPC8260 PowerQUICC II Users Manual MOTOROLA
MOTOROLA Chapter 35. Parallel I/O Ports 35-11
35-12 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 35-6 shows the port B pin assignments.
Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1)
MOTOROLA Chapter 35. Parallel I/O Ports 35-13
Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1) (Continued)
Table 35-7 shows the port C pin assignments.
35-14 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 35-7. Port C Dedicated Pin Assignment (PPARC = 1)
Table 35-6. Port B Dedicated Pin Assignment (PPARB = 1) (Continued)
35-15 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 35-7. Port C Dedicated Pin Assignment (PPARC = 1) (Continued)
35-16 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 35-7. Port C Dedicated Pin Assignment (PPARC = 1) (Continued)
MOTOROLA Chapter 35. Parallel I/O Ports 35-17
Table 35-8 shows the port D pin assignments.
Table 35-8. Port D Dedicated Pin Assignment (PPARD = 1)
35-18 MPC8260 PowerQUICC II Users Manual MOTOROLA
Table 35-8. Port D Dedicated Pin Assignment (PPARD = 1) (Continued)
MOTOROLA Chapter 35. Parallel I/O Ports 35-19
35.6 Interrupts from Port C
Table 35-8. Port D Dedicated Pin Assignment (PPARD = 1) (Continued)
Page
MOTOROLA Appendix A. Register Quick Reference Guide A-1
Appendix A Register Quick Reference Guide
This section provides a brief guide to the core registers.
Table A-2 lists SPRs dened by the PowerPC architecture implemented on the MPC8260.
A.1 PowerPC RegistersUser Registers
Table A-1. User-Level PowerPC Registers (Non-SPRs)
A.2 PowerPC RegistersSupervisor Registers
Table A-4 lists supervisor-level SPRs defined by the PowerPC architecture.
Table A-3. Supervisor-Level PowerPC Registers (Non-SPR)
Table A-4. Supervisor-Level PowerPC SPRs
MOTOROLA Appendix A. Register Quick Reference Guide A-3
A.3 MPC8260-Specic SPRs
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Numerics
A
B
C
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D
E
F
G
H
I
J
L
M
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N
O
P
R
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S
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T
U
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Attention!
