Renesas M32R-FPU manuals
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Renesas M32R-FPU Software Manual
192 pages 473.97 Kb
RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R-FPUwww.renesas.com Software Manual 4 Table of contents42 ADD43 ADD344 ADDIADDIAdd immediateimm8dest0100 ADDI Rdest,#imm8 45 ADDVADDVdest0000 ADDV Rdest,Rsrc1000 Add with overflow checking 46 ADDV3ADDV3 Rdest,Rsrc,#imm16 src1000 dest1000 imm16 ADDV3Add 3-operand with overflow checking 47 ADDXsrc ADDX Rdest,Rsrc Add with carry1001dest0000 ADDX Rdest,Rsrc 48 ANDAND11000000 AND Rdest,Rsrc AND 49 AND350 BCBCBit clear M32R-FPU Extended Instruction Bit clear 51 BCLRBCLR0 src0111 disp16 BCLR #bitpos,@(disp16,Rsrc) 1010 BCLR #bitpos,@(disp16,Rsrc) 52 BEQBEQ3-16 Branch on equal to1011 src1 0000 src2 pcdisp16 BEQ Rsrc1,Rsrc2,pcdisp16 53 BEQZBEQZ3-17 Branch on equal to zero1011 0000 1000 src pcdisp16 BEQZ Rsrc,pcdisp16 54 BGEZBGEZ3-18 Branch on greater than or equal to zero1011 0000 1011 src pcdisp16 BGEZ Rsrc,pcdisp16 55 BGTZBGTZ3-19 Branch on greater than zero1011 0000 1101 src pcdisp16 BGTZ Rsrc,pcdisp16 56 BLBL57 BLEZBLEZ3-21 Branch on less than or equal to zero1011 0000 1100 src pcdisp16 BLEZ Rsrc,pcdisp16 58 BLTZBLTZ3-22 Branch on less than zero1011 0000 1010 src pcdisp16 BLTZ Rsrc,pcdisp16 59 BNCBNC60 BNEBNE3-24 Branch on not equal to1011 src1 0001 src2 pcdisp16 BNE Rsrc1,Rsrc2,pcdisp16 61 BNEZBNEZ3-25 Branch on not equal to zero1011 0000 1001 src pcdisp16 BNEZ Rsrc,pcdisp16 BNEZ Rsrc,pcdisp16 62 BRABRA63 BSETBSET3-27 bit operation Instructions 0 src0110 disp16 Bit setBSET #bitpos,@(disp16,Rsrc) 1010 BSET #bitpos,@(disp16,Rsrc) 64 BTSTBTST65 CLRPSWCLRPSW3-29 bit operation Instructions imm8 Clear PSWCLRPSW #imm8 00100111 CLRPSW #imm8 66 CMP67 CMPICMPI Rsrc,#imm16 Compare immediate1000 0000 0100 src imm16 CMPI Rsrc,#imm16 68 CMPU69 CMPUICMPUI Rsrc,#imm16 Compare unsigned immediate1000 0000 0101 src imm16 CMPUI Rsrc,#imm16 dest1001 src0000 00000000 00000000 DIV Rdest,Rsrc 70 DIV71 DIVUDIVU Rdest,Rsrc Divide unsigneddest1001 src0001 00000000 00000000 DIVU Rdest,Rsrc 72 FADDFADDFADD Rdest,Rsrc1,Rsrc2 Floating-point addsrc11101 src20000 dest0000 00000000 FADD Rdest,Rsrc1,Rsrc2 73 FADDFADD3-37 Floating-point addd 3-38 74 FCMPFCMPsrc11101 src20000 dest0000 00001100 FCMP Rdest,Rsrc1,Rsrc2 FCMP Rdest,Rsrc1,Rsrc2floating point Instructions Floating-point compare 75 FCMPFCMP3-39 Floating-point compare 3-40 76 FCMPEFCMPEsrc11101 src20000 dest0000 00001101 FCMPE Rdest,Rsrc1,Rsrc2 FCMPE Rdest,Rsrc1,Rsrc2 Floating-point compare with exception if unordered 77 FCMPEFCMPE3-41 Floating-point compare with exception if unordered 3-42 78 FDIVFDIVFDIV Rdest,Rsrc1,Rsrc2 Floating-point dividesrc11101 src20000 dest0010 00000000 FDIV Rdest,Rsrc1,Rsrc2 79 FDIVFDIV3-43 DIV0: Zero Divide Exception Floating-point divide 3-44 80 FMADDFMADDFMADD Rdest,Rsrc1,Rsrc2 Floating-point multiply and addsrc11101 src20000 dest0011 00000000 FMADD Rdest,Rsrc1,Rsrc2 81 FMADDFMADD3-45 Value after Addition Operation Floating-point multiply and add 82 FMADDFMADD3-46 Value after Addition Operation Floating-point multiply and add 3-47 83 FMSUBFMSUBFMSUB Rdest,Rsrc1,Rsrc2 Floating-point multiply and subtractsrc11101 src20000 dest0011 00000100 FMSUB Rdest,Rsrc1,Rsrc2 84 FMSUBFMSUB3-48 Value after Subtraction Operation Floating-point multiply and subtract 85 FMSUBFMSUB3-49 Value after Subtraction Operation Floating-point multiply and subtract 3-50 86 FMULFMULFMUL Rdest,Rsrc1,Rsrc2 Floating-point multiplysrc11101 src20000 dest0001 00000000 FMUL Rdest,Rsrc1,Rsrc2 87 FMULFMUL3-51 Floating-point multiply 3-52 88 FSUBFSUBFSUB Rdest,Rsrc1,Rsrc2 Floating-point subtractsrc11101 src20000 dest0000 00000100 FSUB Rdest,Rsrc1,Rsrc2 89 FSUBFSUB3-53 Floating-point subtract 3-54 90 FTOIFTOIFTOI Rdest,Rsrc Float to Integersrc1101 00000000 dest0100 00001000 FTOI Rdest,Rsrc 91 FTOIFTOI3-55 Float to Integer 3-56 92 FTOSFTOSFTOS Rdest,Rsrc Float to shortsrc1101 00000000 dest0100 00001100 FTOS Rdest,Rsrc 93 FTOSFTOS94 ITOFITOFITOF Rdest,Rsrc Integer to floatsrc1101 00000000 dest0100 00000000 ITOF Rdest,Rsrc 95 JLJL3-59 Jump and linkJL Rsrc 11100001 JL Rsrcsrc1100 96 JMPJMP3-60 JumpJMP Rsrc JMP Rsrc11110001 1100 src 97 LDLD98 LD24LD243-62 Load 24-bit immediateLD24 Rdest,#imm24 dest1110 imm24 LD24 Rdest,#imm24 99 LDBLDB100 LDHLDH101 LDILDI102 LDUBLDUB103 LDUHLDUH104 LOCKLOCK3-68 Load lockedLOCK Rdest,@Rsrc dest0010 LOCK Rdest,@Rsrcsrc1101 105 MACHIMACHI3-69 Multiply-accumulate high-order halfwords MACHI Rsrc1,Rsrc2 src10011 MACHI Rsrc1,Rsrc2src20100 106 MACLOMACLO3-70 Multiply-accumulate low-order halfwords MACLO Rsrc1,Rsrc2 src10011 MACLO Rsrc1,Rsrc2src20101 107 MACWHIMACWHI3-71 Multiply-accumulate word and high-order halfwordMACWHI Rsrc1,Rsrc2 src10011 MACWHI Rsrc1,Rsrc2src20110 108 MACWLOMACWLO3-72 Multiply-accumulate word and low-order halfwordMACWLO Rsrc1,Rsrc2 src10011 MACWLO Rsrc1,Rsrc2src20111 109 MULMUL3-73 MUL Rdest,Rsrc dest0001 MUL Rdest,Rsrcsrc0110 110 MULHIMULHI3-74 Multiply high-order halfwordsMULHI Rsrc1,Rsrc2 MULHI Rsrc1,Rsrc2src10011 src20000 111 MULLOMULLO3-75 Multiply low-order halfwordsMULLO Rsrc1,Rsrc2 src10011 MULLO Rsrc1,Rsrc2src20001 112 MULWHIMULWHI3-76 DSP function instruction word and high-order halfwordMULWHI Rsrc1,Rsrc2 src10011 MULWHI Rsrc1,Rsrc2src20010 113 MULWLOMULWLO3-77 DSP fucntion instruction word and low-order halfwordMULWLO Rsrc1,Rsrc2 src10011 MULWLO Rsrc1,Rsrc2src20011 114 MVMV3-78 Move registerMV Rdest,Rsrc dest0001 MV Rdest,Rsrcsrc1000 115 MVFACHIMVFACHI3-79 Move high-order wordMVFACHI Rdest dest0101 MVFACHI Rdest00001111 116 MVFACLOMVFACLO3-80 Move low-order wordMVFACLO Rdest dest0101 MVFACLO Rdest00011111 117 MVFACMIMVFACMI3-81 DSP function instruction Move middle-order wordMVFACMI Rdest dest0101 MVFACMI Rdest00101111 118 MVFCMVFC3-82 Move from control registerMVFC Rdest,CRsrc dest0001 MVFC Rdest,CRsrcsrc1001 119 MVTACHIMVTACHI3-83 Move high-order word to accumulatorMVTACHI Rsrc src0101 MVTACHI Rsrc00000111 120 MVTACLOMVTACLO3-84 Move low-order word to accumulatorMVTACLO Rsrc src0101 MVTACLO Rsrc00010111 121 MVTCMVTC3-85 Move to control registerMVTC Rsrc,CRdest dest0001 MVTC Rsrc,CRdestsrc1010 122 NEGNEG3-86 NegateNEG Rdest,Rsrc dest0000 NEG Rdest,Rsrcsrc0011 123 NOPNOP124 NOTNOT3-88 Logical NOTNOT Rdest,Rsrc dest0000 NOT Rdest,Rsrcsrc1011 125 OROR3-89 OROR Rdest,Rsrc dest0000 OR Rdest,Rsrcsrc1110 126 OR3OR33-90 OR 3-operandOR3 Rdest,Rsrc,#imm16 dest1000 src1110 imm16 OR3 Rdest,Rsrc,#imm16 127 RACRAC3-91 Round accumulator 128 RACRAC3-92 [Supplement] This instruction is executed in two steps as shown below: <step 1> <step 2> Round accumulator 129 RACHRACH3-93 Round accumulator halfwordRACH RACH00000101 00001000 130 RACHRACH3-94 [Supplement] This instruction is executed in two steps, as shown below. <proccess 1> <proccess 2> Round accumulator halfword 131 REMREM3-95 RemainderREM Rdest,Rsrc dest1001 src0010 00000000 00000000 REM Rdest,Rsrc 132 REMUREMU3-96 Remainder unsignedREMU Rdest,Rsrc dest1001 src0011 00000000 00000000 REMU Rdest,Rsrc 133 RTERTE3-97 EIT-related instruction Return from EIT 134 SETHSETH135 SETPSWSETPSW3-99 Bit Operation Instructions 00010111 imm8 SETPSW #imm8 Set PSW 136 SLLSLL3-100 Shift left logicalSLL Rdest,Rsrc dest0001 src0100 SLL Rdest,Rsrc 137 SLL3SLL3Shift left logical 3-operand 138 SLLISLLI3-102 Shift left logical immediateSLLI Rdest,#imm5 dest0101 imm5010 SLLI Rdest,#imm5 139 SRASRA3-103 Shift right arithmeticSRA Rdest,Rsrc dest0001 src0010 SRA Rdest,Rsrc 140 SRA3SRA3Shift right arithmetic 3-operand 141 SRAISRAI3-105 Shift right arithmetic immediateSRAI Rdest,#imm5 dest0101 imm5001 SRAI Rdest,#imm5 142 SRLSRL3-106 Shift right logicalSRL Rdest,Rsrc dest0001 src0000 SRL Rdest,Rsrc 143 SRL3SRL3Shift right logical 3-operand 144 SRLISRLI3-108 Shift right logical immediateSRLI Rdest,#imm5 dest0101 imm5000 SRLI Rdest,#imm5 145 STST3-109 Store(1) ST Rsrc1,@Rsrc2 (2) ST Rsrc1,@+Rsrc2 (3) ST Rsrc1,@-Rsrc2 (4) ST Rsrc1,@(disp16,Rsrc2) 146 STST147 STBSTB148 STHSTHStore halfword [M32R-FPU Extended Mnemonic] 149 SUBSUB3-113 SubtractSUB Rdest,Rsrc dest0000 0010 src SUB Rdest,Rsrc 150 SUBVSUBV3-114 Subtract with overflow checkingSUBV Rdest,Rsrc dest0000 0000 src SUBV Rdest,Rsrc 151 SUBXSUBX3-115 Subtract with borrowSUBX Rdest,Rsrc dest0000 0001 src SUBX Rdest,Rsrc 152 TRAPTRAP3-116 EIT-related instruction TrapTRAP #imm4 0001 0000 1111 imm4 TRAP #imm4; 153 UNLOCKUNLOCK3-117 Store unlockedUNLOCK Rsrc1,@Rsrc2 src10010 UNLOCK Rsrc1,@Rsrc2src20101 154 UTOFUTOF3-118 Floating Point Instructions Unsigned integer to floatUTOF Rdest,Rsrc src1101 00000000 dest0100 00000100 UTOF Rdest,Rsrc 155 XORXOR3-119 Exclusive ORXOR Rdest,Rsrc dest0000 XOR Rdest,Rsrcsrc1101 156 XOR3XOR33-120 Exclusive OR 3-operandXOR3 Rdest,Rsrc,#imm16 dest1000 1101 src imm16 XOR3 Rdest,Rsrc,#imm16 158 Appendix1 Hexadecimal Instraction CodeFPU extended instruction (b0-b3 = 1101, b8-b11 = 0000)0 1101 0000 b16-b19 b24-b27 b0-b3b8-b11 16-bit instruction b0-b3b8-b11 32-bit instruction APPENDIX 1Appendix 1 Hexadecimal Instraction Code0000 0001 0010 0011 0100 0101 0110 0111 01 234 567 1 2 3 4 5 6 7 APPENDICES-3 159 APPENDIX 1Appendix 1 Hexadecimal Instraction Code1000 1001 1010 1011 1100 1101 1110 1111 01 234 567 1 2 3 4 5 6 7 0 APPENDICES-4 160 Appendix 2 Instruction List164 Appendix 3 Pipeline ProcessingAppendix Figure 3.1.1 Instructions and Pipeline Process Appendix Figure 3.1.1 shows each instruction type and the pipeline process. Appendix 3.1 Instructions and Pipeline Processing 165 APPENDICES-9 166 APPENDICES-10 Appendix Figure 3.2.1 Pipeline Flow with no Stall (1) Appendix 3.2 Pipeline Basic Operation 167 APPENDICES-11 Appendix Figure 3.2.2 Pipeline Flow with no Stall (2) 168 APPENDICES-12 LD R3,@R4<Case 1> An instruction which requires several cycles is executed in E DIV R1,R2 ADD R3,R4 ADD R5,R6 ADD R7,R8<Case 2> An instruction which requires more than 1 cycle for its operand access is executed LD R1,@R2 ADD R5,R6 ADD R7,R8 Appendix Figure 3.2.3 Pipeline Flow with Stalls (1) 169 APPENDICES-13 Appendix Figure 3.2.4 Pipeline Flow with Stalls (2) 170 APPENDICES-14 Appendix Figure 3.2.5 Pipeline Flow with Stalls (3) 171 APPENDICES-15 Appendix Figure 3.2.6 Pipeline Flow with Stalls (4) 172 APPENDICES-16 Appendix Figure 3.2.7 Pipeline Flow with Stalls (5) APPENDICES-17 173 Appendix 4 Instruction Execution TimeAPPENDIX 4Appendix 4 Instruction Execution Time APPENDICES-18 174 Appendix 5 IEEE754 Specification Overview179 Appendix 6 M32R-FPU Specification Supplemental Explanation185 Appendix 7 PrecautionsAppendix 7.1 Precautions to be taken when aligning data APPENDIX 7Appendix 7 Precautions INDEX-2 188 SymbolA B C D 189 LM O P E F G H I 190 RS T U
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