Renesas M32R-FPU APPENDICES-24

APPENDICES

APPENDICES-24 M32R-FPU Software Manual (Rev.1.01)

(1) Overflow occurs in Step 1

<When EO = 0, EX = 0: OVF and IXCT occur>

Type of R0 Condition FMUL + FADD Operation FMADD Operation

Normalized –R0 = OVF immediate R0 = OVF immediate

number, 0 value (Note 1) + R0 value (Note 2)

Infinity when OVF immediate value EV=0 IVLD occurs same as left

R0=H'7FFF FFFF

is R0 and the opposite sign EV=1 IVLD occurs, EIT occurs same as left

of the infinity sign R0 = maintained

factors other than above –R0 = ∞same as left

(same as original value)

Denormalized DN=0 UIPL occurs, EIT occurs same as left

number R0 = maintained

DN=1 R0 = OVF immediate value same as left

(Note 1)

QNaN –R0 = maintained (QNaN) same as left

SNaN EV=0 IVLD occurs same as left

R0 = R0 converted to QNaN

EV=0 IVLD occurs, EIT occurs same as left

R0 = maintained (SNaN)

Note 1: Refer to [Appendix Table 5.3.1 Operation Result due to OVF Exception] for immediate

values if an overflow occurs due to Overflow Exclusion when the EIT processing is

masked.

Note 2: In Step 1, the rounding mode is set to [Round toward 0]. However, when an overflow

occurs, the immediate value is rounded according to the rounding mode. Refer to

[Appendix Table 5.3.1 Operation Result due to OVF Exception] for these values.

However, when the rounding mode is [round toward nearest], the OVF immediate value =

infinity and the R0 value becomes the same as that of FMUL + FADD.

<When EO = 1: OVF occurs>

Type of R0 Condition FMUL + FADD Operation FMADD Operation

Normalized –EIT occurs when FMUL is EIT occurs,

number, 0, completed R0 = maintained

Infinity R0 = maintained

Denormalized DN=0 Same as above UIPL occurs,

number EIT occurs

R0 = maintained

DN=1 Same as above EIT occurs

R0 = maintained

QNaN –Same as above Same as above

SNaN EV=0 Same as above IVLD occurs,

EIT occurs

R0 = maintained

EV=1 Same as above Same as above

APPENDIX 6

Appendix 6 M32R-FPU Specification Supplemental Explanation

Contents

Main RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER REJ09B0112-0101Z M32R-FPU www.renesas.com Software Manual Keep safety first in your circuit designs! Notes regarding these materials REVISION HISTORY M32R-FPU Software Manual R1 (1) Table of contents CHAPTER 1 CPU PROGRAMMING MODEL CHAPTER 2 INSTRUCTION SET CHAPTER 3 INSTRUCTIONS APPENDIX (2) INDEX Page Page 1-2 1.1 CPU Register 1.1 CPU Register 1.2 General-purpose Registers 1-3 1.3 Control Registers 1-4 1.3.1 Processor Status Word Register: PSW (CR0) 1-5 1.3.2 Condition Bit Register: CBR (CR1) 1.3.3 Interrupt Stack Pointer: SPI (CR2) User Stack Pointer: SPU (CR3) 1.3.4 Backup PC: BPC (CR6) 1-6 1.3.5 Floating-point Status Register: FPSR (CR7) 1-7 1-8 1.3.6 Floating-point Exceptions (FPE) 1-9 1-10 1-11 1.4 Accumulator 1.4 Accumulator 1.5 Program Counter 1-12 1.6 Data Format Figure 1.6.1 Data Type 1.6.1 Data Type 1-13 1.6.2 Data Format 1-14 1-15 1.7 Addressing Mode 1.7 Addressing Mode Page Page 2-2 2.1 Instruction set overview 2.1.1 Load/store instructions 2-3 Page Page Page 2-7 Page 2-9 Fig. 2.1.2 DSP function instruction operation 1 (multiply, multiply and accumulate) 2-10 Note: The actual operation is processed in two steps. Refer to Chapter 3 for details. Fig. 2.1.3 DSP function instruction operation 2 (round off) Fig. 2.1.4 DSP function instruction operation 3 (transfer between accumulator and register) Page 2-12 2.2 Instruction format 2.2 Instruction format Fig. 2.2.2 Instruction format of M32R CPU Fig. 2.2.1 16-bit instruction and 32-bit instruction 2-13 2.2 Instruction format Page Page 3-2 3.1 Conventions for instruction description 3.1 Conventions for instruction description + - / % ++ -- Page 3-4 3.1 Conventions for instruction description 3-5 3.2 Instruction description ADD ADD Add ADD3 Add 3-operand 3-8 ADDI ADDI Rdest,#imm8 ADDI Add immediate imm8dest0100 ADDI Rdest,#imm8 3-9 ADDV ADDV Rdest,Rsrc src ADDV dest0000 ADDV Rdest,Rsrc1000 Add with overflow checking 3-10 ADDV3 ADDV3 Rdest,Rsrc,#imm16 src1000 dest1000 imm16 ADDV3 Add 3-operand with overflow checking ADDV3 Rdest,Rsrc,#imm16 3-11 ADDX src ADDX Rdest,Rsrc Add with carry 1001dest0000 ADDX Rdest,Rsrc ANDAND 11000000 AND Rdest,Rsrc AND srcdest AND Rdest,Rsrc AND3 AND 3-operand BCBC Bit clear M32R-FPU Extended Instruction 3-15 bit operation Bit clear BCLRBCLR 0 src0111 disp16 BCLR #bitpos,@(disp16,Rsrc) 1010 BCLR #bitpos,@(disp16,Rsrc) BEQBEQ 3-16 Branch on equal to 1011 src1 0000 src2 pcdisp16 BEQ Rsrc1,Rsrc2,pcdisp16 BEQZBEQZ 3-17 Branch on equal to zero 1011 0000 1000 src pcdisp16 BEQZ Rsrc,pcdisp16 BGEZBGEZ 3-18 Branch on greater than or equal to zero 1011 0000 1011 src pcdisp16 BGEZ Rsrc,pcdisp16 BGTZBGTZ 3-19 Branch on greater than zero 1011 0000 1101 src pcdisp16 BGTZ Rsrc,pcdisp16 BLBL Branch and link BLEZBLEZ 3-21 Branch on less than or equal to zero 1011 0000 1100 src pcdisp16 BLEZ Rsrc,pcdisp16 BLTZBLTZ 3-22 Branch on less than zero 1011 0000 1010 src pcdisp16 BLTZ Rsrc,pcdisp16 BNCBNC Branch on not C-bit BNEBNE 3-24 Branch on not equal to 1011 src1 0001 src2 pcdisp16 BNE Rsrc1,Rsrc2,pcdisp16 BNEZBNEZ 3-25 Branch on not equal to zero 1011 0000 1001 src pcdisp16 BNEZ Rsrc,pcdisp16 BRABRA Branch BSETBSET 3-27 bit operation Instructions 0 src0110 disp16 BTSTBTST Bit test CLRPSWCLRPSW 3-29 bit operation Instructions imm8 Clear PSW CMP Compare 3-31 CMPI CMPI Rsrc,#imm16 compare instruction Compare immediate 1000 0000 0100 src imm16 CMPI Rsrc,#imm16 CMPU Compare unsigned 3-33 CMPUI CMPUI Rsrc,#imm16 compare instruction Compare unsigned immediate 1000 0000 0101 src imm16 CMPUI Rsrc,#imm16 DIV Divide DIV Rdest,Rsrc 3-35 DIVU DIVU Rdest,Rsrc Divide unsigned dest1001 src0001 00000000 00000000 DIVU Rdest,Rsrc 3-36 FADDFADD FADD Rdest,Rsrc1,Rsrc2 Floating-point add src11101 src20000 dest0000 00000000 FADD Rdest,Rsrc1,Rsrc2 FADDFADD 3-37 Floating-point addd 3-38 FCMPFCMP src11101 src20000 dest0000 00001100 FCMP Rdest,Rsrc1,Rsrc2 FCMP Rdest,Rsrc1,Rsrc2 floating point Instructions Floating-point compare FCMPFCMP 3-39 Floating-point compare 3-40 FCMPEFCMPE src11101 src20000 dest0000 00001101 FCMPE Rdest,Rsrc1,Rsrc2 FCMPE Rdest,Rsrc1,Rsrc2 Floating-point compare with exception if unordered FCMPEFCMPE 3-41 Floating-point compare with exception if unordered 3-42 FDIVFDIV FDIV Rdest,Rsrc1,Rsrc2 Floating-point divide src11101 src20000 dest0010 00000000 FDIV Rdest,Rsrc1,Rsrc2 FDIVFDIV 3-43 DIV0: Zero Divide Exception Floating-point divide 3-44 FMADDFMADD FMADD Rdest,Rsrc1,Rsrc2 Floating-point multiply and add src11101 src20000 dest0011 00000000 FMADD Rdest,Rsrc1,Rsrc2 FMADDFMADD 3-45 Value after Addition Operation Floating-point multiply and add FMADDFMADD 3-46 Value after Addition Operation Floating-point multiply and add 3-47 FMSUBFMSUB FMSUB Rdest,Rsrc1,Rsrc2 Floating-point multiply and subtract src11101 src20000 dest0011 00000100 FMSUB Rdest,Rsrc1,Rsrc2 FMSUBFMSUB 3-48 Value after Subtraction Operation Floating-point multiply and subtract FMSUBFMSUB 3-49 Value after Subtraction Operation Floating-point multiply and subtract 3-50 FMULFMUL FMUL Rdest,Rsrc1,Rsrc2 Floating-point multiply src11101 src20000 dest0001 00000000 FMUL Rdest,Rsrc1,Rsrc2 FMULFMUL 3-51 Floating-point multiply 3-52 FSUBFSUB FSUB Rdest,Rsrc1,Rsrc2 Floating-point subtract src11101 src20000 dest0000 00000100 FSUB Rdest,Rsrc1,Rsrc2 FSUBFSUB 3-53 Floating-point subtract 3-54 FTOIFTOI FTOI Rdest,Rsrc Float to Integer src1101 00000000 dest0100 00001000 FTOI Rdest,Rsrc FTOIFTOI 3-55 Float to Integer 3-56 FTOSFTOS FTOS Rdest,Rsrc Float to short src1101 00000000 dest0100 00001100 FTOS Rdest,Rsrc FTOSFTOS 3-57 Float to short 3-58 ITOFITOF ITOF Rdest,Rsrc Integer to float src1101 00000000 dest0100 00000000 ITOF Rdest,Rsrc JLJL 3-59 Jump and link JL Rsrc 11100001 JL Rsrcsrc1100 JMPJMP 3-60 Jump JMP Rsrc JMP Rsrc11110001 1100 src LDLD Load LD24LD24 3-62 Load 24-bit immediate LD24 Rdest,#imm24 dest1110 imm24 LD24 Rdest,#imm24 LDBLDB Load byte LDHLDH Load halfword LDILDI Load immediate LDUBLDUB Load unsigned byte LDUHLDUH Load unsigned halfword LOCKLOCK 3-68 Load locked LOCK Rdest,@Rsrc dest0010 LOCK Rdest,@Rsrcsrc1101 MACHIMACHI 3-69 Multiply-accumulate high-order halfwords MACHI Rsrc1,Rsrc2 src10011 MACHI Rsrc1,Rsrc2src20100 MACLOMACLO 3-70 Multiply-accumulate low-order halfwords MACLO Rsrc1,Rsrc2 src10011 MACLO Rsrc1,Rsrc2src20101 MACWHIMACWHI 3-71 Multiply-accumulate word and high-order halfword MACWHI Rsrc1,Rsrc2 src10011 MACWHI Rsrc1,Rsrc2src20110 MACWLOMACWLO 3-72 Multiply-accumulate word and low-order halfword MACWLO Rsrc1,Rsrc2 src10011 MACWLO Rsrc1,Rsrc2src20111 MULMUL 3-73 MUL Rdest,Rsrc dest0001 MUL Rdest,Rsrcsrc0110 MULHIMULHI 3-74 Multiply high-order halfwords MULHI Rsrc1,Rsrc2 MULHI Rsrc1,Rsrc2src10011 src20000 MULLOMULLO 3-75 Multiply low-order halfwords MULLO Rsrc1,Rsrc2 src10011 MULLO Rsrc1,Rsrc2src20001 MULWHIMULWHI 3-76 DSP function instruction word and high-order halfword MULWHI Rsrc1,Rsrc2 MULWLOMULWLO 3-77 DSP fucntion instruction word and low-order halfword MULWLO Rsrc1,Rsrc2 MVMV 3-78 Move register MV Rdest,Rsrc dest0001 MV Rdest,Rsrcsrc1000 MVFACHIMVFACHI 3-79 Move high-order word MVFACHI Rdest dest0101 MVFACHI Rdest00001111 MVFACLOMVFACLO 3-80 Move low-order word MVFACLO Rdest dest0101 MVFACLO Rdest00011111 MVFACMIMVFACMI 3-81 DSP function instruction Move middle-order word MVFACMI Rdest MVFCMVFC 3-82 Move from control register MVFC Rdest,CRsrc dest0001 MVFC Rdest,CRsrcsrc1001 MVTACHIMVTACHI 3-83 Move high-order word to accumulator MVTACHI Rsrc src0101 MVTACHI Rsrc00000111 MVTACLOMVTACLO 3-84 Move low-order word to accumulator MVTACLO Rsrc src0101 MVTACLO Rsrc00010111 MVTCMVTC 3-85 Move to control register MVTC Rsrc,CRdest dest0001 MVTC Rsrc,CRdestsrc1010 NEGNEG 3-86 Negate NEG Rdest,Rsrc dest0000 NEG Rdest,Rsrcsrc0011 NOPNOP 3-87 No operation NOP NOP00000111 00000000 NOTNOT 3-88 Logical NOT NOT Rdest,Rsrc dest0000 NOT Rdest,Rsrcsrc1011 OROR 3-89 OR OR Rdest,Rsrc dest0000 OR Rdest,Rsrcsrc1110 OR3OR3 3-90 OR 3-operand OR3 Rdest,Rsrc,#imm16 dest1000 src1110 imm16 OR3 Rdest,Rsrc,#imm16 RACRAC 3-91 Round accumulator RAC RAC00000101 00001001 RACRAC 3-92 [Supplement] This instruction is executed in two steps as shown below: <step 1> <step 2> DSP function instruction RACHRACH 3-93 Round accumulator halfword RACH RACH00000101 00001000 RACHRACH 3-94 [Supplement] This instruction is executed in two steps, as shown below. <proccess 1> <proccess 2> DSP function instruction REMREM 3-95 Remainder REM Rdest,Rsrc dest1001 src0010 00000000 00000000 REM Rdest,Rsrc REMUREMU 3-96 Remainder unsigned REMU Rdest,Rsrc dest1001 src0011 00000000 00000000 REMU Rdest,Rsrc RTERTE 3-97 EIT-related instruction Return from EIT RTE SETHSETH Set high-order 16-bit SETPSWSETPSW 3-99 Bit Operation Instructions 00010111 imm8 SETPSW #imm8 Set PSW SLLSLL 3-100 Shift left logical SLL Rdest,Rsrc dest0001 src0100 SLL Rdest,Rsrc SLL3SLL3 Shift left logical 3-operand SLLISLLI 3-102 Shift left logical immediate SLLI Rdest,#imm5 dest0101 imm5010 SLLI Rdest,#imm5 SRASRA 3-103 Shift right arithmetic SRA Rdest,Rsrc dest0001 src0010 SRA Rdest,Rsrc SRA3SRA3 Shift right arithmetic 3-operand SRAISRAI 3-105 Shift right arithmetic immediate SRAI Rdest,#imm5 dest0101 imm5001 SRAI Rdest,#imm5 SRLSRL 3-106 Shift right logical SRL Rdest,Rsrc dest0001 src0000 SRL Rdest,Rsrc SRL3SRL3 Shift right logical 3-operand SRLISRLI 3-108 Shift right logical immediate SRLI Rdest,#imm5 dest0101 imm5000 SRLI Rdest,#imm5 STST 3-109 Store (1) ST Rsrc1,@Rsrc2 (2) ST Rsrc1,@+Rsrc2 (3) ST Rsrc1,@-Rsrc2 (4) ST Rsrc1,@(disp16,Rsrc2) STST STBSTB Store byte STHSTH Store halfword [M32R-FPU Extended Mnemonic] SUBSUB 3-113 Subtract SUB Rdest,Rsrc dest0000 0010 src SUB Rdest,Rsrc SUBVSUBV 3-114 Subtract with overflow checking SUBV Rdest,Rsrc dest0000 0000 src SUBV Rdest,Rsrc SUBXSUBX 3-115 Subtract with borrow SUBX Rdest,Rsrc dest0000 0001 src SUBX Rdest,Rsrc TRAPTRAP 3-116 EIT-related instruction Trap TRAP #imm4 UNLOCKUNLOCK 3-117 Store unlocked UNLOCK Rsrc1,@Rsrc2 src10010 UNLOCK Rsrc1,@Rsrc2src20101 UTOFUTOF 3-118 Floating Point Instructions Unsigned integer to float UTOF Rdest,Rsrc XORXOR 3-119 Exclusive OR XOR Rdest,Rsrc dest0000 XOR Rdest,Rsrcsrc1101 XOR3XOR3 3-120 Exclusive OR 3-operand XOR3 Rdest,Rsrc,#imm16 dest1000 1101 src imm16 XOR3 Rdest,Rsrc,#imm16 Page APPENDICES-2 Appendix1 Hexadecimal Instraction Code FPU extended instruction (b0-b3 = 1101, b8-b11 = 0000) 0 1101 0000 b16-b19 b24-b27 b0-b3b8-b11 APPENDIX 1 Appendix 1 Hexadecimal Instraction Code 1000 1001 1010 1011 1100 1101 1110 1111 01 234 567 1 2 3 4 5 6 7 0 APPENDICES-4 Appendix 2 Instruction List The M32R-FPU instruction list is shown below (in alphabetical order). APPENDICES-5 APPENDICES-6 Page APPENDICES-8 Appendix 3 Pipeline Processing Appendix Figure 3.1.1 Instructions and Pipeline Process Appendix Figure 3.1.1 shows each instruction type and the pipeline process. Appendix 3.1 Instructions and Pipeline Processing APPENDICES-9 APPENDICES-10 Appendix Figure 3.2.1 Pipeline Flow with no Stall (1) Appendix 3.2 Pipeline Basic Operation APPENDICES-11 Appendix Figure 3.2.2 Pipeline Flow with no Stall (2) APPENDICES-12 LD R3,@R4 <Case 1> An instruction which requires several cycles is executed in E DIV R1,R2 ADD R3,R4 APPENDICES-13 Appendix Figure 3.2.4 Pipeline Flow with Stalls (2) APPENDICES-14 Appendix Figure 3.2.5 Pipeline Flow with Stalls (3) APPENDICES-15 Appendix Figure 3.2.6 Pipeline Flow with Stalls (4) APPENDICES-16 Appendix Figure 3.2.7 Pipeline Flow with Stalls (5) APPENDICES-17 Appendix 4 Instruction Execution Time APPENDIX 4 Appendix 4 Instruction Execution Time APPENDICES-18 Appendix 5 IEEE754 Specification Overview Appendix 5.1 Floating Point Formats APPENDICES-19 APPENDICES-20 Appendix 5.2 Rounding Appendix 5.3 Exceptions APPENDICES-21 APPENDICES-22 APPENDICES-23 Appendix 6 M32R-FPU Specification Supplemental Explanation APPENDICES-24 APPENDICES-25 (2) When underflow occurs in Step 1 <When EU = 0, DN = 1: UDF occurs> <When EU = 0, DN = 0: UDF and UIPL occur> <When EU = 1: UDF occurs> APPENDICES-26 APPENDICES-27 APPENDICES-28 Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU APPENDICES-29 Appendix 7 Precautions Appendix 7.1 Precautions to be taken when aligning data APPENDIX 7 Appendix 7 Precautions Page Page INDEX-2 Symbol A B C D L M O P E R S T U