Renesas M32R-FPU APPENDICES-22

APPENDICES
APPENDICES-22 M32R-FPU Software Manual (Rev.1.01)
APPENDIX 5
Appendix 5 IEEE754 Specification Overview
(5) Invalid Operation Exception (IVLD)
The exception occurs when an invalid operation is executed. Appendix Table 5.3.5
shows operation results and the respective conditions in which each IVLD occurs.
Appendix Table 5.3.5 Operation Results due to IVLD Exception
Result
Occurrence Condition when the IVLD EIT when the IVLD EIT
processing is masked processing is executed
Operation for SNaN operand QNaN (Destination unchanged)
+Infinity– (+Infinity), –Infinity– (–Infinity)
0 ✕ Infinity
0 ÷ 0, Infinity ÷ Infinity
oute operation for values less then 0
Integer conversion overflow: Undefined
NaN and ∞ are converted to integers
When < or > comparison was performed on NaN (No change)
Important: The following operations never generate an Exception.
√ (-0): returns –0
∞/ 0: returns ∞ (Sign of result is exclusive-OR (EXOR) of signs of divider and
dividend.)
■ Definition of Terms
• Exception
Special conditions generated by execution of floating-point instructions. The
corresponding enable bits of the floating-point status register are used to determine
whether the EIT processing will be executed when an Exception occurs. However, the
actual generation of an exception cannot be masked.
• EIT Processing
An operation triggered by the generation of an Exception, in which the flow jumps to a
floating-point Exception vector address, or a string of related Exception operation
sequences is triggered. The corresponding enable bits of the floating-point status
register are used to determine whether the EIT processing will be executed when an
Exception occurs.
• Intermediate Result of Operation
The value resulting from calculations of infinite and unbounded exponent and mantissa
bits. In actual implementation, the number of exponent and mantissa bits is finite and
the intermediate result is rounded so that the final operation result can be determined.