ADCP-61-471 • Issue 4 • June 2000 • Section 2: Operation and Maintenance

TAD-104

Page 7 of 11

HS

 

HS

 

HS

HS

HS

HS

HSW

HSP

EQ

 

UNEQ

 

IS

OSS

PROT

UNPROT

RESET

RESET

 

1

 

2

3

4

5

6

7

8

 

 

 

 

 

 

 

 

 

 

SW TO

 

SW TO

 

HS NET

HS NET

HS A NET

HS A NET

HS B NET

HS B NET

HSW

 

HSP

 

LPBK ON

LPBK OFF

LPBK ON

LPBK OFF

LPBK ON

LPBK OFF

 

9

 

10

11

12

13

14

15

16

 

 

 

 

 

 

 

 

 

 

HS APS

 

HS APS

 

HS CL

 

 

 

 

 

ENAB

 

DIS

 

APS

 

 

 

 

 

 

 

 

 

LOCK

 

 

 

 

 

 

17

 

18

19

20

21

22

23

24

 

 

 

 

 

 

 

 

 

 

HS CUS

 

HS CUS

 

HS A CUS

HS A CUS

HS B CUS

HS B CUS

 

 

LPBK

 

LPBK

 

LPBK

LPBK

LPBK

LPBK

 

 

ON

 

OFF

 

ON

OFF

ON

OFF

 

 

 

25

 

26

27

28

29

30

31

32

 

 

 

 

 

 

 

 

 

 

MX

 

MX

 

MX

MX

MX TX

MX TX

MX

MX

EQ

 

UNEQ

 

IS

OSS

LBO IN

LBO OUT

PROT

UNPROT

 

33

 

34

35

36

37

38

39

40

 

 

 

 

 

 

 

 

 

 

SW TO

 

SW TO

 

MX NET

MX NET

MX CUS

MX CUS

MXW

MXP

MXW

 

MXP

 

LPBK

LPBK

LPBK

LPBK

RESET

RESET

 

 

 

 

ON

OFF

ON

OFF

 

 

 

41

 

42

43

44

45

46

47

48

 

 

 

 

 

 

 

 

 

 

MX APS

 

MX APS

 

MX CL

 

 

 

 

 

ENAB

 

DIS

 

APS

 

 

 

 

 

 

 

 

 

LOCK

 

 

 

 

 

 

49

 

50

51

52

53

54

55

56

 

 

 

 

 

 

 

 

 

 

ACO

 

MPU

 

 

 

 

 

 

ATT

 

 

RESET

 

 

 

 

 

 

RESERVED

 

57

 

58

59

60

61

62

63

64

 

 

 

 

 

 

 

 

 

 

Note: Bit definitions for High Speed (HS) or MUX (MX) modules are not significant when the MPU is installed in the Soneplex Loop Extender chassis.

Figure 104-3. Command Display 1

2-272

© 2000, ADC Telecommunications, Inc.