ADC Z8F04A08100KIT user manual Connector JP1

Z8F04A08100KIT

User Manual

PA0_JP

R11

PA0_MDS

Note 1:

VCC_33V

D2

LED_G

JP2

connector 2

2

1

If Module is plugged onto the Dev Platform the local

VCC_33V

RS232 interface is disabled by pin 50 of JP2

100

LED

GREEN

DEMO

USER

1

2

R12

3

4

5

6

10K

1 2 3

J3

VCC_33V

7

8

GND

9

10

11

12

Header 3

13

14

S1

PA0

J4

15

16

PA0_MDS

1

17

18

GND

1

2

PA3_CTS

0

DBG

DBG

GND

19

20

PA1_MDS

2

TEST

PA1_JP

21

22

PA2_MDS

R13

D3

HEADER 2

23

24

LED_Y

PA1_MDS

25

26

2

1

VCC_33V

27

28

GND

LED

29

30

100

31

32

YEL

DEMO

USER

R14

PA3_MDS

33

34

PA5_MDS

PA4_MDS

35

36

1 2 3

10K

37

38

J5

GND

39

40

PA1

41

42

Header 3

GND

SW1

43

44

PA2_JP

PA2_MDS

45

46

GND

R15

D4

RESET

47

48

49

50

-DIS_232

2

1

LED_R

51

52

-DIS_IrDA

-DIS_IRDA

-RESET

-RESET

53

54

PA0_JP

100

LED

RED

DEMO

USER

VCC_33V

55

56

GND

C13

57

58

PA1_JP

VCC_33V

59

60

1 2 3

J6

R16

R17

PA2

HEADER 30x2/SM

8 pin footprint

Header 3

J7

0

0

U5

1

Connector JP1

VCC_33V

1

8

GND

2

VDD

VSS

RESET

PA3_JP

PA0

2

PA0

PA5

7

PA5_JP

HEADER 2

for reference

PA1

3

6

PA4_JP

PA3_CTS0

PA3_CTS

0

PA1

PA4

PA3_MDS

PA2_JP

4

PA2

PA3

5

PA3_JP

only

DEMO

USER

Z8F04xA_8pin

JP1

1

2

1 2 3

J8

-TRSTN

3

4

PA3

5

6

R19

R20

Header 3

-F91_WE

7

8

VCC_33V

PA4_JP

GND

9

10

0

0

PA4_RXD0

PA4_RXD

0

PA4_MDS

A6

11

12

A0

R21

A10

13

14

A3

DEMO

USER

GND

15

16

VCC_33V

A8

17

18

A7

220K

A13

19

20

A9

Y1

1 2 3

A15

21

22

A14

J9

A18

23

24

A16

1

1

3

3

PA4

A19

25

26

GND

Header 3

A2

27

28

A1

2

PA5_JP

PA5_MDS

A11

29

30

A12

C10

C11

PA5_TXD0

PA5_TXD0

A4

31

32

A20

20 MHz

DEMO

USER

A5

33

34

A17

2

35

36

-DIS_FLASH

NOTE 2

A21

37

38

VCC_33V

A22

39

40

A23

1 2 3

J10

-CS0

41

42

-CS1

-CS2

43

44

D0

PA5

D1

45

46

D2

Header 3

D3

47

48

D4

TABLE 1

D5

49

50

GND

Note 2:

D7

51

52

D6

The XP supports internal oscillator, external crystal, or ceramic

-MREQ

53

54

-IOREQ

resonator, external R/C and external CMOS drive clock modes. R16,

GND

55

56

-RD

Clock Mode

R16

R17

R19

R20

R21

C10

C11

Y1

-

-WR

57

58

-INSTRD

R17, R19, R20, R21, C10, C11 and Y1 are used to support the clock mode

BUSACK 59

60

-BUSREQ

Internal

Note 2

Note 2

none

none

none

none

none

none

selected. The development board is

shipped configured for internal

oscillator. When

using

internal

oscilator, pins 2 and 3 could be used

HEADER 30x2/SM

Ceramic Res

none

none

0 Ohm

0 Ohm

220K

10-20pF

10-20pF

user

as GPIO ports PA0 and

PA1. Table 1 shows the recommended clock mode

select

configurations.

Crystal

none

none

0 Ohm

0 Ohm

220K

10-20 pF

10-20 pF

user

select

8pin MDS Processor Module. Schematic.

Number

Rev

96C0964-001

B

December 14, 2004

Sheet

2

of

2

Schematic, Z8 Encore! XP™ 4K Series 8-Pin MCU Development Board, Page 2 of 2

18

UM018702-0505