Status Byte Register
This register summarizes the information from all other status groups as defined in the "IEEE 488.2 Standard Digital Interface for Programmable Instrumentation" standard. The bit configuration is shown in Table
The RQS Bit
Whenever the power supply requests service, it sets the SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller services the interrupt, RQS is cleared inside the register and returned in bit position 6 of the response. The remaining bits of the Status Byte register are not disturbed.
The MSS Bit
This is a
Determining the Cause of a Service Interrupt
You can determine the reason for an SRQ by the following actions:
•Use a serial poll or the *STB? query to determine which summary bits are active.
•Read the corresponding Event register for each summary bit to determine which events caused the summary bit to be set. When an Event register is read, it is cleared. This also clears the corresponding summary bit.
•The interrupt will recur until the specific condition that caused each event is removed. If this is not possible, the event may be disabled by programming the corresponding bit of the status group Enable register or NTRPTR filter. A faster way to prevent the interrupt is to disable the service request by programming the appropriate bit of the Service Request Enable register.
Service Request Enable Register
This register is a mask that determines which bits from the Status Byte register will be ORed to generate a service request (SRQ). The register is programmed with the *SRE common command. When the register is cleared, no service requests can be generated to the controller.
Output Queue
The Output Queue is a
Initial Conditions At Power On
Status Registers
When the power supply is turned on, a sequence of commands initializes the status registers. For the
54 Status Reporting