AMD Turion™ 64 Mobile Technology Product Data Sheet
•Compatible with Existing
| – Including support for SSE, SSE2, SSE3*, MMX™, |
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| 3DNow!™ technology, and legacy x86 instructions | |||
| *SSE3 supported by Rev. E and later processors | • Refer to the AMD Functional Data Sheet, | ||
| – Runs existing operating systems and drivers | |||
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| – Local APIC on the chip |
| mechanical, and electrical details of | |
• | AMD64 Technology |
| packages. | |
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| – AMD64 technology instruction set extensions | • | Packaging | |
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| – Eight additional |
| – 29 x | |
| – Eight additional |
| – 40 mm x 40 mm organic substrate | |
• | Enhanced Virus Protection |
| – Organic C4 die attach | |
| – No Execute (NX) bit in | • | Integrated Memory Controller | |
| specifies whether code can be executed from the |
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• HyperTransport™ Technology to I/O Devices |
| – Supports up to two unbuffered |
–One
•
–Two
•
–With advanced branch prediction
•
L2 Cache
–Exclusive cache
–Up to 1 Mbyte per L2 cache
–1 Mbyte and
•Machine Check Architecture
–Includes hardware scrubbing of major
•Electrical Interfaces
–HyperTransport™ technology:
–DDR SDRAM: SSTL_2 per JEDEC specification
–Clock, reset, and test signals also use DDR
•Power Management
–Multiple
–System Management Mode (SMM)
–ACPI compliant, including support for processor performance states
–AMD PowerNow!™ technology is designed to dynamically switch between multiple
Publication # | 32816 | Revision: | 3.05 |
Issue Date: | September 2006 |
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