| B85 Pro4 |
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| RAS# to CAS# Delay (tRCD) |
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The number of clock cycles required between the opening of a row of memory and |
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accessing columns within it. |
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| Row Precharge Time (tRP) |
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The number of clock cycles required between the issuing of the precharge command |
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and opening the next row. |
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| RAS# Active Time (tRAS) |
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The number of clock cycles required between a bank active command and issuing the |
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precharge command. |
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| Command Rate (CR) |
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The delay between when a memory chip is selected and when the first active command can |
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be issued. |
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| Write Recovery Time (tWR) |
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The amount of delay that must elapse after the completion of a valid write operation, |
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before an active bank can be precharged. |
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| Refresh Cycle Time (tRFC) |
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The number of clocks from a Refresh command until the first Activate command to |
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the same rank. |
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| RAS to RAS Delay (tRRD) |
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The number of clocks between two rows activated in different banks of the same |
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rank. |
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| Write to Read Delay (tWTR) |
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The number of clocks between the last valid write operation and the next read |
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command to the same internal bank. |
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| Read to Precharge (tRTP) |
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The number of clocks that are inserted between a read command to a row pre- |
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charge command to the same rank. |
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English | |||
| Four Activate Window (tFAW) | |||
The time window in which four activates are allowed the same rank. | |||
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