English
Command Rate (CR)
The delay between when a memory chip is selected and when the first active command can be issued.
Write Recovery Time (tWR)
The amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged.
Refresh Cycle Time (tRFC)
The number of clocks from a Refresh command until the first Activate command to the same rank.
RAS to RAS Delay (tRRD)
The number of clocks between two rows activated in different banks of the same rank.
Write to Read Delay (tWTR)
The number of clocks between the last valid write operation and the next read command to the same internal bank.
Read to Precharge (tRTP)
The number of clocks that are inserted between a read command to a row pre- charge command to the same rank.
Four Activate Window (tFAW)
The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Configure CAS Write Latency.
tREFI
Configure refresh cycles at an average periodic interval.
tCKE
Configure the period of time the DDR3 initiates a minimum of one refresh command internally once it enters
tRDRD
Configure between module read to read delay.
60
