MTRR Mappi ng [ Conti nuous]

This option determines the method used for programming CPU MTRRs when 4GB or more of memory is present. Discrete leaves the PCI hole below the 4GB boundary undescribed. Continuous explicitly describes the PCI hole as non-caheable. Configuration options: [Continuous] [Discrete]

Runti me Legacy PSB [ Di sabl ed]

Enables or disables the generation of Power State Block for use of PowerNow(tm) driver in a single core system.

Configuration options: [Disabled] [Enabled]

ACPI 2.0 Objects [Enabl ed]

Enables or disables the generation of ACPI_PPC, _PSS, and _PCT objects. Configuration options: [Disabled] [Enabled]

2.4.2 Chi pset

The Chipset menu allows you to change the advanced chipset settings. Select an item then press <Enter> to display the sub-menu.

Advanced Chipset Settings

WARNING: Setting wrong values in below sections may cause the system to malfunction.

NorthBridge Configuration

Southbridge

Hyper Transport Configuration

NorthBridge Configuration

North Bridge chipset Configuration

Memory Configuration

 

Memclock Mode

[Auto]

MCT Timing Mode

[Auto]

Enable Clock to ALL DIMMs

[Disabled]

MemCLK Tristate C3/ATLVID

[Disabled]

Memory Hole Remapping

[Enabled]

Power Down Control

[Auto]

2-20

Chapter 2: BIOS setup