Asus P3B-F 4.4.1Chip Configuration, SETUP BIOS, SDRAM CAS Latency, DRAM Idle Timer [10T], SDRAM RAS to CAS Delay, SDRAM RAS Precharge Time, SDRAM Configuration [By SPD]

4.BIOS SETUP

4.4.1Chip Configuration

SETUP BIOS .4

Configuration Chip

SDRAM Configuration [By SPD]

This sets the optimal timings for items 2–4, depending on the memory modules that you are using. Default setting is [By SPD], which configures items 2–4 by reading the contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module stores critical parameter information about the module, such as memory type, size, speed, voltage interface, and module banks. Configuration options: [User Define] [7ns (143MHz)] [8ns (125MHz)] [By SPD]

SDRAM CAS Latency

This controls the latency between the SDRAM read command and the time that the data actually becomes available. NOTE: To make changes to this field, the SDRAM Configuration field must be set to [User Define].

SDRAM RAS to CAS Delay

This controls the latency between the SDRAM active command and the read/write command. NOTE: To make changes to this field, the SDRAM Configuration field must be set to [User Define].

SDRAM RAS Precharge Time

This controls the idle clocks after issuing a precharge command to the SDRAM. NOTE: To make changes to this field, the SDRAM Configuration field must be set to [User Define].

DRAM Idle Timer [10T]

This controls the amount of time in HCLKs that the DRAM controller waits to close a DRAM page after the CPU becomes idle. Leave on default set- ting. NOTE: To make changes to this field, the SDRAM Configuration field must be set to [User Define]. Configuration options: [0T] [2T] [4T] [8T] [10T] [12T] [16T] [32T] [Infinite]

54 ASUS P3B-F User’s Manual