tRR (DD) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clockt
RR (DR) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock] tRRSR [Auto]
Configuration options: [Auto] [4 DRAM Clock] – [7 DRAM Clock] tWW (DD) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock] tWW (DR) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [8 DRAM Clock] tWWSR [Auto]
Configuration options: [Auto] [4 DRAM Clock] – [7 DRAM Clock]
MISC
MRC Fst Boot [Enabled]
Configuration options: [Enabled] [Disabled]
DRAM CLK Period [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [14 DRAM Clock]
Transmitter Slew (CHA) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [7 DRAM Clock]
Transmitter Slew (CHB) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [7 DRAM Clock]
Receiver Slew (CHA) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [7 DRAM Clock]
Receiver Slew (CHB) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [7 DRAM Clock]
MCH Duty Sense (CHA) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [31 DRAM Clock]
MCH Duty Sense (CHB) [Auto]
Configuration options: [Auto] [1 DRAM Clock] – [31 DRAM Clock]
Channel A DIMM Control [Enable Both DIMMS]
Configuration options: [Enable Both DIMMS] [Disable DIMM0] [Disable DIMM1] [Disable Both DIMMS]
Channel B DIMM Control [Enable Both DIMMS]
Configuration options: [Enable Both DIMMS] [Disable DIMM0] [Disable DIMM1] [Disable Both DIMMS]
Chapter 3