forces a watchdog reset by addressing the Module and requesting sufficient information to cause a minimum of 65 clock line transitions. Advantages to the trapping routine are:
•The bombed processor is detected before erroneous values
•The processor may be reset sooner.
•The time of processor failure may be logged by the datalogger.
•Number of failures may be logged.
A trapping routine, as described above, is included in the example program in the Appendix.
8.Measurement Applications
8.1SPDT Switch Closure
(0 V). Switch bounce may occur any number of times at a throw, but until contact is made with the opposite throw, a change in state will not occur. The pole must make contact with the throw for 3 ms for a state change to occur. Figure 3 illustrates a raw SPDT signal in relation to the signal conditioned by the SW8A.
FIGURE 3. SPDT Signal Conditioning by
NOTE The 5V output located next to each of the 8 input channels is for biasing in the SPDT measurement. A 200 Ohm resistor is in series to protect against accidental shorting to ground.
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