Technical Reference Guide
Compaq Deskpro 4000N and 4000S Personal Computers
First Edition – September 1997
ix
LIST OF TABLESTABLE 1–1. ACRONYMS AND ABBREVIATIONS.......................................................................................1-3
TABLE 2–1. ARCHITECTURAL COMPARISON.............................................................................................2-8
TABLE 2–2. SUPPORT CHIPSETS .......................................................................................................... 2-11
TABLE 2–3. GRAPHICS SUBSYSTEM OVERVIEW....................................................................................2-12
TABLE 2–4. ENVIRONMENTAL SPECIFICATIONS....................................................................................2-13
TABLE 2–5. ELECTRICAL SPECIFICATIONS........................................................................................... 2-13
TABLE 2–6. PHYSICAL SPECIFICATIONS...............................................................................................2-13
TABLE 2–7. DISKETTE DRIVE SPECIFICATIONS.....................................................................................2-14
TABLE 2–8. 8X CD-ROM DRIVE SPECIFICATIONS................................................................................2-14
TABLE 2–9. HARD DRIVE SPECIFICATIONS...........................................................................................2-15
TABLE 3–1. PROCESSOR/MEMORY ARCHITECTURAL HIGHLIGHTS............................................................3-1
TABLE 3–2. PENTIUM MMX MICROPROCESSOR BUS/CORE SPEED SWITCH SETTINGS.............................3-4
TABLE 3–3. SW1 BUS/CORE SPEED POSITIONS TO GPIO ASSIGNMENTS...................................................3-4
TABLE 3–4. SDRAM PERFORMANCE TIMES............................................................................................3-5
TABLE 3–5. SPD ADDRESS MAP (SDRAM DIMM).................................................................................3-6
TABLE 3–6. HOST/PCI BRIDGE CONFIGURATION REGISTERS (VT82C595)..............................................3-8
TABLE 4–1. 32-BIT PCI BUS CONNECTOR PINOUT.................................................................................4-3
TABLE 4–2. PCI BUS MASTERING DEVICES...........................................................................................4-4
TABLE 4–3. PCI DEVICE CONFIGURATION ACCESS................................................................................4-6
TABLE 4–4. PCI FUNCTION CONFIGURATION ACCES..............................................................................4-7
TABLE 4–5. PCI DEVICE IDENTIFICATION............................................................................................. 4-8
TABLE 4–6. PCI/ISA BRIDGE CONFIGURATION REGISTERS FOR THE VT82C586 (P55C-BASED SYSTEMS)4-10
TABLE 4–7. ISA EXPANSION CONNECTOR PINOUT............................................................................... 4-12
TABLE 4–8. DEFAULT DMA CHANNEL ASSIGNMENTS......................................................................... 4-15
TABLE 4–9. DMA PAGE REGISTER ADDRESSES................................................................................... 4-16
TABLE 4–10. DMA CONTROLLER REGISTERS......................................................................................4-17
TABLE 4–11. MASKABLE INTERRUPT PRIORITIES AND ASSIGNMENTS.................................................... 4-19
TABLE 4–12. MASKABLE INTERRUPT CONTROL REGISTERS.................................................................. 4-19
TABLE 4–13. INTERVAL TIMER FUNCTIONS ......................................................................................... 4-22
TABLE 4–14. INTERVAL TIMER CONTROL REGISTERS...........................................................................4-22
TABLE 4–15. CLOCK GENERATION AND DISTRIBUTION (PENTIUM-BASED SYSTEM)...............................4-23
TABLE 4–16. CONFIGURATION MEMORY (CMOS) MAP.......................................................................4-25
TABLE 4–17. SYSTEM I/O MAP...........................................................................................................4-41
TABLE 4–18. 87307 I/O CONTROLLER PNP STANDARD CONTROL REGISTERS........................................ 4-42
TABLE 4–19. SYSTEM MANAGEMENT CONTROL REGISTERS................................................................... 4-44
TABLE 5–1. IDE PCI CONFIGURATION REGISTERS................................................................................5-2
TABLE 5–2. IDE BUS MASTER CONTROL REGISTERS............................................................................. 5-2
TABLE 5–3. IDE ATA CONTROL REGISTERS.........................................................................................5-3
TABLE 5–4. IDE CONTROLLER COMMANDS.......................................................................................... 5-6
TABLE 5–5. 40-PIN IDE CONNECTOR PINOUT....................................................................................... 5-8
TABLE 5–6. 40-PIN IDE CONNECTOR PINOUT....................................................................................... 5-9
TABLE 5–7. DISKETTE DRIVE CONTROLLER CONFIGURATION REGISTERS............................................. 5-11
TABLE 5–8. DISKETTE DRIVE CONTROLLER REGISTERS....................................................................... 5-12
TABLE 5–9. 34-PIN DISKETTE DRIVE CONNECTOR PINOUT...................................................................5-14
TABLE 5–10. DB-9 SERIAL CONNECTOR PINOUT.................................................................................5-15
TABLE 5–11. SERIAL INTERFACE CONFIGURATION REGISTERS..............................................................5-16