CyberResearch® CPU Cards | CPEX Series |
Hardware Prefetcher: [Disabled]
A third mechanism used to reduce the time waiting for DRAM is through a
Adjacent Cache Line Prefetch [Disabled]
This menu allows you to enable or disable the adjacent cache line prefetch mode. Configuration options: [Disabled] [Enabled]
Hyper-Threading Technology [Enabled]
This item allows you to enable or disable the processor
Configuration options: [Disabled] [Enabled]
IDE Configuration
The items in this menu allow you to set or change the configurations for the IDE devices installed in the system. Select an item then press Enter if you wish to configure the item.
ATA/IDE Configuration [Compatible]
This item allows you to configure the ATA/IDE.
Configuration options: [Disabled] [Compatible] [Enhanced]
Legacy IDE Channels [SATA Pri, PATA Sec]
Primary and Secondary IDE Master/Slave
While CPEX series is turned ON, the BIOS auto detects the presence of IDE devices. This menu, when entered, shows detail information of the IDE devices (Device type, Vendor, Size, LBA Mode, Block Mode, PIO Mode, Async DMA, Ultra DMA, and SMART monitoring). This information is
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