Clocks

1.Ensure that the XTALSLC[1:0] pin levels correspond to the frequency of the signal at XTALIN and XTALOUT.

2.Leave the XTALOUT floating if an external clock source is used.

3.Clock or crystal characteristics must conform to the requirements specified in the data sheet.

4.The design must adhere to the power supply noise specifications for the PLL specified in the data sheet.

5.XVDDQ is the select pin for crystal and clock. XVDDQ must be 3.3V when using a crystal. XVDDQ must be 1.8V when using a clock source as an input.

Table 5 lists the various clock selection input settings.

Table 5. Clock Selection Input Settings

 

XTALSLC[1]

 

 

XTALSLC[0]

 

 

Clock

 

 

Crystal

 

 

 

 

 

 

Frequency

 

 

Support

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

 

19.2 MHz

 

Yes

 

 

 

 

 

 

 

 

0

 

1

 

 

24 MHz

 

Yes

 

 

 

 

 

 

 

 

1

 

0

 

 

48 MHz

 

No

 

 

 

 

 

 

 

 

1

 

1

 

 

26 MHz

 

Yes

 

 

 

 

 

 

 

 

 

 

 

 

Decoupling for Power Supplies

1.VDD requires 2.2 µF and 0.1 µF decoupling.

2.Although AVDDQ is tied to the same supply as VDD, route it separately with 0.01 µF and 0.1 µF capacitors.

3.UVDDQ requires 2.2 µF and 0.1 µF decoupling.

4.GVDDQ, PVDDQ, SSVDDQ, SNVDDQ, and XVDDQ do not have any specific decoupling requirements. Combine them with the decoupling for other supplies at the same level. If in doubt, use 2.2 µF and 0.1 µF.

AN46860

Miscellaneous

All unused output-only pins may be left floating, but do not leave unused input-only and input/output pins floating. Tie the unused input-only and input/output to a valid logic level using a single 10k pull up resistor. There is a negligible difference if the unused input-only pins are tied HIGH or LOW. For lowest leakage, tie unused input/output pins HIGH.

Ensure that all unused pins handled in this manner are tied to their corresponding power domain. For example, an unused GPIO[1] is tied HIGH to GVDDQ through a 10k pull up, which is shared with other unused signals in the GVDDQ power domain.

Astoria is not hardware backward compatible to Antioch. So, if the system is designed in Antioch, it requires PCB change when replaced by Astoria.

About the Author

Name:

Praveen Kumar

Title:Applications Engineer

Contact: prku@cypress.com.

5B

December 12, 2008

Document No. 001-46860 Rev. *A

3

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Cypress AN46860 Clocks, Decoupling for Power Supplies, Miscellaneous, About the Author, Clock Crystal Frequency Support
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AN46860 specifications

The Cypress AN46860 is a versatile and high-performance microcontroller that belongs to the PSoC (Cypress's Programmable System-on-Chip) family. This device is designed to cater to the demands of various embedded applications, providing developers with a unique blend of programmable analog and digital resources. The AN46860 is particularly well-suited for applications in automotive, industrial, and consumer electronics due to its robust feature set and reliable performance.

One of the standout features of the AN46860 is its flexible architecture. The microcontroller integrates a 32-bit ARM Cortex-M4 processor, which allows for efficient processing and handling of complex tasks. With clock speeds reaching up to 100 MHz, the AN46860 is capable of executing multiple instructions in parallel, significantly increasing its computational capabilities.

Another significant advantage of the AN46860 is its wide range of programmable analog and digital peripherals. The device includes various analog components, such as operational amplifiers, comparators, and high-resolution ADCs (Analog-to-Digital Converters). These components enable precise signal processing, making the microcontroller ideal for applications that require real-time data acquisition and conversion.

The digital side of the AN46860 boasts ample connectivity options, including multiple GPIOs, UART, SPI, I2C, and PWM, enabling seamless communication with other devices and peripherals. This makes it easier for developers to integrate the microcontroller into existing systems or to create new, innovative designs.

One of the highlights of the AN46860 is its programmability. The PSoC architecture allows developers to tailor the hardware functionality through software, a feature that can significantly reduce development time and costs. The device supports the Cypress PSoC Creator Integrated Development Environment (IDE), which provides a user-friendly interface and a rich library of pre-defined components, enabling developers to drag-and-drop their way to a custom solution.

Additionally, the AN46860 features a built-in bootloader to facilitate firmware updates and enhancements, ensuring that applications can be easily upgraded in the field. It also offers low-power modes that help extend battery life in portable applications, making it an attractive choice for energy-conscious designs.

In summary, the Cypress AN46860 is a powerful microcontroller with a blend of programmable analog and digital features, making it highly adaptable for various applications. Its combination of a robust processing core, extensive peripheral support, and flexibility through software programmability ensures that it meets the needs of today’s demanding technology landscape.
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