CY25818/19
3-Level Digital Inputs
S0 digital input is designed to sense three logic levels desig- nated as HIGH “1,” LOW “0,” and MIDDLE “M.” With this
The S0 pin includes an
Logic Level “0”:
Logic Level “M”:
Logic Level “1”:
LO G IC | LO G IC | LO G IC | |||||
LO W (0) | M ID D LE (M ) | H IG H (H ) | |||||
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| V D D | |
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S 0 |
| S0 |
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| S 0 |
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to VSS | U N C O NN EC TED | to V DD | |||||
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Modulation Rate
Spread Spectrum Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rates of SSCG clocks are generally referred to in terms of frequency, and fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider determine the Modulation Rate.
In the case of CY25818/19 devices, the (Spread Spectrum) Modulation Rate, fmod, is given by the following formula:
fmod = fIN/DR
where fmod is the Modulation Rate, fIN is the Input Frequency, and DR is the Divider Ratio, as given in Table 3.
V S S
Figure 1.
Table 3. Modulation Rate Divider Ratios
Product |
| Input Frequency Range |
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| Divider Ratio (DR) |
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CY25818 |
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| 256 |
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CY25819 |
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| 512 |
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Maximum Ratings[1, 2] |
| Input Voltage Relative to Vss: |
| Vss + 0.3V | |||||||
Supply Voltage (Vdd): | + 5.5V | Operating Temperature: |
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| 0°C to + 70°C | ||||||
Storage Temperature: |
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Input Voltage Relative to Vdd: | Vdd + 0.3V |
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Table 4. DC Electrical Characteristics Vdd = 3.3V ±10%, TA = 0°C to +70°C and CL = 15 pF (unless otherwise noted) | |||||||||||
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Parameter | Description | Conditions |
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| Min. | Typ. |
| Max. |
| Unit | |
Vdd | Power Supply Range |
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| 2.97 | 3.3 |
| 3.63 |
| V | ||
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VINH | Input HIGH Voltage | S0 Input |
| 0.85 Vdd | Vdd |
| Vdd |
| V | ||
VINM | Input MIDDLE Voltage | S0 Input |
| 0.40 Vdd | 0.50 Vdd |
| 0.60 Vdd |
| V | ||
VINL | Input LOW Voltage | S0 Input |
| 0.0 | 0.0 |
| 0.15 Vdd |
| V | ||
VOH1 | Output HIGH Voltage | IOH = 4 ma, SSCLK and REFCLK | 2.4 | – |
| – |
| V | |||
VOH2 | Output HIGH Voltage | IOH = 6 ma, SSCLK and REFCLK | 2.0 | – |
| – |
| V | |||
VOL1 | Output LOW Voltage | IOL = 4 ma, SSCLK Output |
| – | – |
| 0.4 |
| V | ||
VOL2 | Output LOW Voltage | IOL = 10 ma, SSCLK Output |
| – | – |
| 1.2 |
| V | ||
CIN1 | Input Capacitance | XIN (Pin 1) and XOUT (Pin 8) | 6.0 | 7.5 |
| 9.0 |
| pF | |||
CIN2 | Input Capacitance | All Digital Inputs |
| 3.5 | 4.5 |
| 6.0 |
| pF | ||
IDD1 | Power Supply Current | FIN=8 MHz, no load |
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| – | 10.0 |
| 12.5 |
| mA | |
IDD3 | Power Supply Current | FIN=32 MHz, no load |
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| – | 19.0 |
| 23.0 |
| mA | |
IDD4 | Power Supply Current | PD# = Vss |
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| – | 150 |
| 250 |
| mA |
Document #: | Page 3 of 7 |
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