Manuals / Brands / Computer Equipment / Computer Keyboard / Cypress / Computer Equipment / Computer Keyboard

Cypress CY7C1246V18, CY7C1248V18, CY7C1250V18, CY7C1257V18 TAP Controller

1 27

Download 27 pages, 642.76 Kb

CY7C1246V18, CY7C1257V18

CY7C1248V18, CY7C1250V18

Document Number: 001-06348 Rev. *D Page 15 of 27

TAP Controller Block Diagram

TAP Electrical Characteristics

Over the Operating Range[10, 11, 12]

Parameter Description Test Conditions Min Max Unit

VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V

VOH2 Output HIGH Voltage IOH = −100 μA1.6 V

VOL1 Output LOW Voltage IOL = 2.0 mA 0.4 V

VOL2 Output LOW Voltage IOL = 100 μA0.2V

VIH Input HIGH Voltage 0.65VDD VDD + 0.3 V

VIL Input LOW Voltage –0.3 0.35VDD V

IXInput and Output Load Current GND ≤ VI ≤ VDD −55μA

0

012..

29

3031

Boundary Scan Register

Identification Register

012..

.

.

108

012

Instruction Register

Bypass Register

Selection

Circuitry Selection

Circuitry

TAP Controller

TDI TDO

TCK

TMS

Notes

10.These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page20.

11.Overshoot: VIH(AC) < VDDQ + 0.3V (pulse width less than tCYC/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than tCYC/2).

12.All voltage refers to ground.

[+] Feedback [+] Feedback

Contents

Main CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations Functional Description Selection Guide CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Document Number: 001-06348 Rev. *D Page 2 of 27 Logic Block Diagram (CY7C1246V18) Logic Block Diagram (CY7C1257V18) 2M x 8 Array 2M x 8 Array Logic Block Diagram (CY7C1248V18) Logic Block Diagram (CY7C1250V18) 1M x 18 Array 1M x 18 Array 512K x 36 Array 512K x 36 Array CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Configurations CY7C1246V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1257V18 (4M x 9) CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Configurations CY7C1248V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1250V18 (1M x 36) CY7C1246V18, CY7C1257V18 Pin Definitions CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Pin Definitions CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Functional Overview Read Operations Write Operations Byte Write Operations Application Example Truth Table BUS MASTER (CPU or ASIC) SRAM#1 SRAM#2 Page Page CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 IEEE 1149.1 Serial Boundary Scan (JTAG) Disabling the JTAG Feature Test Access Port Test Clock Test Mode Select Page TAP Controller State Diagram TAP Controller Block Diagram TAP Controller TAP Electrical Characteristics TAP AC Switching Characteristics TAP Timing and Test Conditions Test Clock Test Mode Select TCK TMS Test Data In TDI Test Data Out TDO Identification Register Definitions Scan Register Sizes Instruction Codes CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Boundary Scan Order Power Up Sequence in DDR-II+ SRAM Power Up Sequence Clock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) DLL Constraints Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Input Requirements Capacitance Thermal Resistance AC Test Loads and Waveforms Switching Characteristics Document Number: 001-06348 Rev. *D Page 23 of 27 Switching Waveforms Read/Write/Deselect Sequence READ NOP WRITE READ READ 12345678910 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Ordering Information CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 Ordering Information Document Number: 001-06348 Rev. *D Page 26 of 27 Package Diagram [+] Feedback [+] Feedback Figure 6. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195 51-85195-*A Document History Page